IPC분류정보
국가/구분 |
United States(US) Patent
등록
|
국제특허분류(IPC7판) |
|
출원번호 |
UP-0399272
(2006-04-05)
|
등록번호 |
US-7676529
(2010-04-21)
|
발명자
/ 주소 |
- Del Riccio, Jr., John Emedio
- Wougk, Harald Alexander
- Migliaccio, Anthony Frank
|
출원인 / 주소 |
- Pine Valley Investments, Inc.
|
대리인 / 주소 |
|
인용정보 |
피인용 횟수 :
0 인용 특허 :
11 |
초록
▼
A system and method is provided for converting an input signal from a sequence of rectangular coordinate pairs to a sequence of polar coordinate pairs. The input signal includes a sequence of input vectors each including a pair of rectangular coordinates. A plurality of N input registers is configur
A system and method is provided for converting an input signal from a sequence of rectangular coordinate pairs to a sequence of polar coordinate pairs. The input signal includes a sequence of input vectors each including a pair of rectangular coordinates. A plurality of N input registers is configured to store an input vector of the input signal. The system includes a plurality of N CORDIC algorithm instances, each in communication with a corresponding one of the N input registers. Each CORDIC algorithm instance is configured to receive the input vector stored in the corresponding input register and to convert the received input vector to a corresponding output vector including a pair of polar coordinates. A recombiner is configured to receive the N output vectors and to recombine at least the N output vectors in sequence to form an output signal.
대표청구항
▼
The invention claimed is: 1. A system for processing an input signal including a sequence of input vectors, each input vector including a pair of rectangular coordinates, the system comprising: a first input register configured to store a first input vector of the input signal; a second input regis
The invention claimed is: 1. A system for processing an input signal including a sequence of input vectors, each input vector including a pair of rectangular coordinates, the system comprising: a first input register configured to store a first input vector of the input signal; a second input register configured to store a second input vector of the input signal; at least one processor communicatively coupled to said first and second input registers, said processor configured to execute; a first CORDIC algorithm instance operative to receive the first input vector and to convert the first input vector to a first output vector including a first pair of polar coordinates, and a second CORDIC algorithm instance operative to receive the second input vector and to convert the second input vector to a second output vector including a second pair of polar coordinates; and a recombiner in communication with the processor and configured to receive the first and second output vectors and to combine at least the first and second output vectors in sequence to form an output signal. 2. The system of claim 1, further comprising: a controller in communication with the first and second input registers, wherein the controller is configured to provide the first input vector to the first input register and to provide the second input vector to the second input register. 3. The system of claim 2, wherein the controller is further configured to provide a control signal to the recombiner, and wherein the recombiner is further configured to sequence the first and second output vectors in accordance with the control signal. 4. The system of claim 1, wherein each pair of output vector polar coordinates includes a magnitude coordinate and a phase coordinate, the system further comprising: a first output register in communication with, the recombiner and configured to receive and store a magnitude component of the output signal, the magnitude component including the magnitude coordinates of the output vectors; and a second output register in communication with the recombiner and configured to receive and store a phase component of the output signal, the phase component including the phase coordinates of the output vectors. 5. The system of claim 1, wherein the first input vector has a bit width of between 9 and 13 bits. 6. The system of claim 1, wherein the first CORDIC algorithm instance is further operative to perform between 8 and 12 iterations in the conversion of the first input vector to a first output vector. 7. A system for processing an input signal including a sequence of at least N input vectors, where N≧2, and wherein each input vector includes a pair of rectangular coordinates, the system comprising: a plurality of N input registers, each configured to store an input vector of the input signal; at least one processor communicatively coupled to said plurality of N input registers, said processor executing a plurality of N CORDIC algorithm instances, each configured to receive the input vector stored in the corresponding input register and to convert the received input vector to a corresponding output vector including a pair of polar coordinates; and a recombiner in communication with said processor, wherein the recombiner is configured to receive the N output vectors and to recombine at least the N output vectors in sequence to form an output signal. 8. A system for processing an input signal including a sequence of at least N input vectors, where N≧2, and wherein each input vector includes a pair of rectangular coordinates, the system comprising: means for storing the input vectors of the input signal; means for performing a plurality of CORDIC conversions in parallel, wherein each CORDIC conversion converts one of the input vectors of the input signal to a corresponding output vector including a pair of polar coordinates; means for recombining the output vectors in sequence to form an output signal. 9. The system of claim 8, further comprising: means for storing a magnitude component of the output signal, the magnitude component including the magnitude coordinates of the output vectors; and means for storing a phase component of the output signal, the phase component including the phase coordinates of the output vectors. 10. The system of claim 8, wherein each of the input vectors has a bit width of between 9 and 13 bits. 11. The system of claim 8, wherein each CORDIC conversion includes between 8 and 12 iterations of a CORDIC algorithm. 12. A method for processing an input signal including a sequence of at least N input vectors, where N≧2, and wherein each input vector includes a pair of rectangular coordinates, the method comprising: Creating N CORDIC algorithm instances of a CORDIC algorithm object; processing each of the first N input vectors using one of the N CORDIC algorithm instances, wherein the nth CORDIC algorithm instance converts the nth input vector to an nth output vector including an nth pair of polar coordinates, and wherein 0≦n≦N−1; and recombining at least the N output vectors in sequence to form an output signal. 13. The method of claim 12, wherein conversion of the nth input vector to the nth output vector includes performing N iterations of the nth CORDIC algorithm. 14. The method of claim 13, wherein a single iteration of the nth CORDIC algorithm is performed during each clock cycle period. 15. The method of claim 13, wherein at least one of the input vectors has a bit width of between 9 and 13 bits. 16. The method of claim 13, wherein the processing of each of the first N input vectors further includes performing between 8 and 12 CORDIC iterations. 17. The method of claim 13, further comprising: beginning to process the first input vector at a time t0; and providing the first converted output vector at a time tN, wherein the time tN is N clock cycle periods after the time t0.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.