$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

Method for manipulating data in a group of processing elements to perform a reflection of the data 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-015/00
출원번호 UP-0689366 (2003-10-20)
등록번호 US-7676648 (2010-04-21)
우선권정보 GB-0309195.6(2003-04-23)
발명자 / 주소
  • Beaumont, Mark
출원인 / 주소
  • Micron Technology, Inc.
대리인 / 주소
    Jones Day
인용정보 피인용 횟수 : 0  인용 특허 : 37

초록

A method for generating a reflection of data in a plurality of processing elements comprises shifting the data along, for example, each row in the array until each processing element in the row has received all the data held by every other processing element in that row. Each processing element stor

대표청구항

What is claimed is: 1. A method for generating a reflection of data in a plurality of processing elements, comprising: shifting the data along either the rows or columns of the plurality of processing elements arranged in an N×N array, where N is greater than three until each processing elemen

이 특허에 인용된 특허 (37)

  1. Crozier George W. (Hatfield PA), Apparatus for high speed image rotation.
  2. Holsztynski Wlodzimierz (Ann Arbor MI) Wilson Stephen S. (Ann Arbor MI), Cellular digital array processor.
  3. Hardwick Jonathan C.,GBX, Dynamic load balancing among processors in a parallel computer.
  4. Wheat Stephen R. (Albuquerque NM), Dynamic load balancing of applications.
  5. Cok Ronald S. (Rochester NY), Enhanced input/output architecture for toroidally-connected distributed-memory parallel computers.
  6. Barker Thomas Norman ; Collins Clive Allan ; Dapp Michael Charles ; Dieffenderfer James Warren ; Knowles Billy Jack ; Lesmeister Donald Michael ; Miles Richard Ernest ; Nier Richard Edward ; Richards, Fully distributed processing memory element.
  7. Ishikawa, Masatoshi; Toyoda, Haruyoshi, High-speed vision sensor with image processing function.
  8. Abercrombie Andrew P. ; Sutha Surachai ; Holsztynski Wlodzimierz, Input/output support for processing in a mesh connected computer.
  9. Rich Henry H., Linear expression evaluator.
  10. Gerald G. Pechanek ; Charles W. Kurak, Jr., Manifold array processor.
  11. Pechanek Gerald G. ; Kurak ; Jr. Charles W., Manifold array processor.
  12. Glover Michael A. (10 Hemlock Way Durham NH 03824), Massively parallel SIMD processor which selectively transfers individual contiguously disposed serial memory elements.
  13. Elliott Duncan G.,CAX ; Snelgrove W. Martin,CAX, Memory device with multiple processors having parallel access to the same memory area.
  14. Pechanek Gerald G. ; Revilla Juan G., Merged array controller and processing element.
  15. Kirsch, Graham, Method and apparatus for a shift register based interconnection for a massively parallel processor array.
  16. David Karger ; Eric Lehman ; F. Thomson Leighton ; Matthew Levine ; Daniel Lewin ; Rina Panagrahy, Method and apparatus for distributing requests among a plurality of resources.
  17. Bratt, Joseph P.; Ouzilevski, Alexei V.; Langhi, Ronald Gerard; Weybrew, Steven Todd, Method and apparatus for matrix transposition.
  18. Kaba James T. C. (Jackson NJ), Method and apparatus for rotating and scaling images.
  19. Ho Ching-Tien (San Jose CA), Method for performing matrix transposition on a mesh multiprocessor architecture having multiple processor with concurre.
  20. Cypher Robert E. (Los Gatos CA) Gravano Luis (Mountain View CA), Method of packet routing in torus networks with two buffers per edge.
  21. Kadakia Vinod K. (Rancho Palos Verdes CA), Method to rotate a bitmap image 90 degrees.
  22. Naganuma Jiro (Zama JPX) Ogura Takeshi (Chigasaki JPX), Multiprocessor system and a method of load balancing thereof.
  23. Hinsley Christopher Andrew,GBX, Operating system for use with computer networks incorporating two or more data processors linked together for parallel processing and incorporating improved dynamic load-sharing techniques.
  24. Miura Hiroki (Takatsuki JPX) Koumura Yasuhito (Nara JPX), Parallel computer system including processing elements.
  25. Miura Hiroki,JPX ; Koumura Yasuhito,JPX, Parallel computer system with error status signal and data-driven processor.
  26. Kenichi Maeda JP; Nobuyuki Takeda JP; Yasukazu Okamoto JP, Parallel computer with improved access to adjacent processor and memory elements.
  27. Mori Kazutaka (Higashiyamato JPX), Parallel data processing system with plural-system bus configuration capable of fast data communication between processo.
  28. Takahashi Fumio (Hitachi JPX) Nagaoka Yukio (Toukai JPX) Harada Twao (Mito JPX), Parallel processing computer including interconnected operation units.
  29. Wilson, Jeremy Craig, Processor array and parallel data processing methods.
  30. Pechanek Gerald G. (Cary NC) Vassiliadis Stamatis (Zoetermeer NLX), Processor using folded array structures for transposition memory and fast cosine transform computation.
  31. Taylor James L. (Eastleigh GBX), SIMD array processor with global instruction control and reprogrammable instruction decoders.
  32. Jonathan Coulombe JP; Seiichiro Iwase JP, SIMD control parallel processor with simplified configuration.
  33. Wilkinson Paul Amba ; Dieffenderfer James Warren ; Kogge Peter Michael ; Schoonover Nicholas Jerome, SIMD/MIMD array processor with vector processing.
  34. Mead Carver A. (San Jose CA) Allen Timothy P. (Mountain View CA), Scanning method and apparatus for current signals having large dynamic range.
  35. Rich Henry H., Shared access texturing of computer graphic images.
  36. Apisdorf, Joel Zvi; Sandbote, Sam Brandon; Poole, Michael Daniel, System and method for data forwarding in a programmable multiple network processor environment.
  37. Matsuoka Hidetoshi (Kawasaki JPX) Hirose Fumiyasu (Kawasaki JPX), Uniform load distributing method for use in executing parallel processing in parallel computer.
섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트

맨위로