IPC분류정보
국가/구분 |
United States(US) Patent
등록
|
국제특허분류(IPC7판) |
|
출원번호 |
UP-0858146
(2007-09-20)
|
등록번호 |
US-7681086
(2010-04-21)
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발명자
/ 주소 |
- Vlassova, Olga Alexandrovna
- Bakowski, Antonio
- Cardoso, Jr., Jaures
- Martinazzo, Aldo
|
출원인 / 주소 |
- Embraer- Empresa Brasileira de Aeronautica S.A.
|
대리인 / 주소 |
|
인용정보 |
피인용 횟수 :
6 인용 특허 :
12 |
초록
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A method for Fault Tree Map generation employs to transformation of Fault Trees of production installation, specific installation, technical system (Hardware and integrated Hardware/Software) to new Fault Tree diagram (Fault Tree Map), which permits drastically compact the Fault Tree depiction and f
A method for Fault Tree Map generation employs to transformation of Fault Trees of production installation, specific installation, technical system (Hardware and integrated Hardware/Software) to new Fault Tree diagram (Fault Tree Map), which permits drastically compact the Fault Tree depiction and facilitates performing of the Fault Tree qualitative analysis, including evaluation of combination of latent failures and evident failures, repeated events and critical events position influence, and failure propagation potentiality, besides facility of localization of each Fault Tree logical Gate and relevant failures in the fault tree printed report. Generation takes place using special symbols, which permit to reflect the Fault Tree logic, present all Fault Tree failures with graphically identification of the failure type, and show the failure repetition and also the failure critically (importance) to Fault Tree Top Event probability. The method presents exceptional advantages to analysis of large-scale, extended Fault Trees, allowing vastly decrease the time of analysis and elevate the analysis quality and Fault Tree perception, including for specialists, who are not the Fault Tree authors.
대표청구항
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We claim: 1. A method of generating a graphical presentation of a fault tree map for use in technical system or installation design and/or diagnostics, said method comprising: (a) creating a fault tree including cut sets and events important evaluation; (b) analyzing the fault tree to determine lat
We claim: 1. A method of generating a graphical presentation of a fault tree map for use in technical system or installation design and/or diagnostics, said method comprising: (a) creating a fault tree including cut sets and events important evaluation; (b) analyzing the fault tree to determine latent failures, repeated events and gates; (c) generating, with a computer, a compact map of said fault tree, said compact map graphically indicating evident event (failure) type with a first connector symbol and indicating events with exposure time in excess of flight duration (mission time) with a second connector symbol different from said first connector symbol; graphically indicating logic gates with predetermined symbols different from Fault Tree gates image; and (d) graphically presenting said compact fault tree map. 2. The method of claim 1 wherein said graphically presenting comprises repeated events and repeated gates with predetermined symbols/colors. 3. The method of claim 1 further including indicating different cut sets with different colors and more important event with predetermined symbols. 4. The method of claim 1 wherein said graphically presenting comprises displaying said compact fault tree map on an electronic display. 5. The method of claim 4 further suppressing from said map, display of word-based events (failures) and gates descriptions. 6. The method of claim 1 further including failure propagation demonstration by color indicating of the propagation path. 7. The method of claim 1 further including numbers of Fault Tree report pages where gates are placed. 8. The method as claimed in claim 1, further including performing fault analysis in production installation. 9. The method as claimed in claim 1, further including performing fault analysis in specific production installation. 10. The method as claimed in claim 1, further including performing fault analysis in technical system/equipment (Hardware). 11. The method as claimed in claim 1, further including performing fault analysis in integrated Hardware/Software technical system. 12. A method for Fault Tree Map generation, with a computer, for a technical system or installation, using as basis the technical system/equipment or installation Fault Tree diagram and comprising: substitution of the all logical Gates by adequate symbols, which graphically define the Gate type and content the Gate identification Code; exclusion of the Gate description; when on the report generation stage, inclusion the numbers of pages, where the logical Gate is placed; substitution of the all evident failures by adequate symbols, which graphically define the failure type; substitution of the all latent failures by adequate symbols (different than evident failure symbols), which graphically define the failure type; substitution of the other types of failures by adequate different symbols, which graphically define the failure types; exclusion of the all evident/latent/other failures description, that permits drastically compact the conventional Fault Tree depiction and facilitates performing of the Fault Tree qualitative analysis including evaluation of combination of latent failures and evident failures, and failure propagation potentiality, besides facility of localization of each Fault Tree logical Gate and relevant failures in the fault tree printed report. 13. The method as claimed in claim 12, further including using computerized means to transform the conventional Fault Tree to a Fault Tree Map. 14. The method as claimed in claim 13, further including using computerized means to automatic indication the relevant information on the Fault Tree Map. 15. The method as claimed in claim 12, further including performing fault analysis in production installation. 16. The method as claimed in claim 12, further including performing fault analysis in specific production installation. 17. The method as claimed in claim 12, further including performing fault analysis in technical system/equipment (Hardware). 18. The method as claimed in claim 12, further including performing fault analysis in integrated Hardware/Software technical system. 19. The method as claimed in claim 12, which further comprises repeated failures and repeated Gates indication, indication of failures utensils to determined Cut Set and indication of the failure importance evaluation results, using special marking, that provide the repeated events consideration and adequate Fault Tree treatment to avoid mistakes; the mitigation means to decrease the importance failure impact to object efficiency and safety. 20. A method of processing a fault tree comprising: (a) analyzing the fault tree to determine latent failures and repeated events; (b) automatically, with a computer, generating a map of said fault tree, said map graphically indicating evident event type with a first connector symbol and indicating events with exposure time in excess of a predetermined duration with a second connector symbol different from said first connector symbol; and (c) graphically presenting said map.
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