IPC분류정보
국가/구분 |
United States(US) Patent
등록
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국제특허분류(IPC7판) |
|
출원번호 |
UP-0389943
(2006-03-27)
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등록번호 |
US-7685216
(2010-04-21)
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발명자
/ 주소 |
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출원인 / 주소 |
- Texas Instruments Incorporated
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대리인 / 주소 |
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인용정보 |
피인용 횟수 :
0 인용 특허 :
7 |
초록
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Recursive digital filter circuitry which avoids persistent unstable conditions therein provides a serial clock signal, a synchronization signal, and a serial data input to corresponding inputs of a 3-wire serial interface circuit to produce a serial clock output signal, a synchronization output sign
Recursive digital filter circuitry which avoids persistent unstable conditions therein provides a serial clock signal, a synchronization signal, and a serial data input to corresponding inputs of a 3-wire serial interface circuit to produce a serial clock output signal, a synchronization output signal, and a parallel data output signal which are applied to corresponding inputs of a recursive digital filter. The serial clock signal and the synchronization signal are input to an auto-reset circuit which detects a fault associated with the synchronization signal or the serial clock signal and produces a reset signal in response to detection of the fault for resetting the recursive digital filter.
대표청구항
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What is claimed is: 1. Auto-resetting recursive digital filter circuitry comprising: a three-wire serial interface circuit receiving a serial clock input signal, a synchronization input signal, and a serial data input signal, and, in response thereto, producing a serial clock output signal, a synch
What is claimed is: 1. Auto-resetting recursive digital filter circuitry comprising: a three-wire serial interface circuit receiving a serial clock input signal, a synchronization input signal, and a serial data input signal, and, in response thereto, producing a serial clock output signal, a synchronization output signal, and a parallel data output signal; a recursive digital filter circuit coupled to receive the serial clock output signal, the synchronization output signal, and the parallel data output signal and, in response thereto, producing a filtered over-sampled data output signal; and an input fault detection circuit having first and second inputs coupled to receive the serial clock input signal and the synchronization input signal, respectively, for detecting a fault associated with one of the synchronization input signal and the serial clock input signal and producing a reset signal coupled to reset the recursive digital filter circuit in response to detection of the fault. 2. The auto-resetting recursive digital filter circuit of claim 1 wherein the input fault detection circuit determines whether a ratio of the frequency of the serial clock input signal to the frequency of the synchronization input signal is equal to an oversampling ratio N between the serial clock input signal and the synchronization input signal and produces the reset signal to reset the recursive digital filter circuit if the ratio is not equal to the oversampling ratio. 3. The auto-resetting recursive digital filter circuit of claim 2 wherein the reset signal resets the recursive digital filter circuit by resetting a register of the recursive digital filter circuit. 4. The auto-resetting recursive digital filter circuit of claim 2 wherein the three-wire serial interface circuit produces a value of the parallel data output signal which is a zero order hold signal. 5. The auto-resetting recursive digital filter circuit of claim 1 wherein the recursive digital filter includes a SYNCN filter coupled to receive the zero order hold signal, wherein the zero order hold signal and the SYNCN filter function to provide a SYNC(N+1) filtering function. 6. The auto-resetting recursive digital filter circuit of claim 2 wherein the oversampling ratio N is equal to 16. 7. The auto-resetting recursive digital filter circuit of claim 2 wherein the three-wire serial interface circuit includes a first group of N flip-flops and a second group of N flip-flops, an input of a first flip-flop of the first group being coupled to receive the serial data input signal, an output of each flip-flop of the first group except a last flip-flop of the first group being coupled to an input of a next succeeding flip-flop of the first group, clock inputs of each of the flip-flops of the first group receiving the serial clock input signal, outputs of each flip-flop of the first group being coupled to an input of a corresponding flip-flop, respectively, of the second group, each flip-flop of the second group being clocked in response to the synchronization input signal, outputs of the flip-flops of the second group producing the parallel data output signal. 8. The auto-resetting recursive digital filter circuitry of claim 7 wherein each of the flip-flops of the first group and each of the flip-flops of the second group are D type flip-flops. 9. The auto-resetting recursive digital filter circuitry of claim 2 wherein the input fault detection circuit includes a pulse generation circuit operable in response to the synchronization input signal to produce an internal reset signal in response to corresponding edges successive pulses of the synchronization input signal, a counter circuit that is operable to advance a count therein in response to each pulse of the serial clock input signal, the counter circuit being resettable in response to the internal reset signal, the input fault detection circuit including a decoding circuit for recognizing whether or not N pulses of the serial clock input signal have occurred between successive internal reset signals and latching a state indicative of whether or not N pulses of the serial clock input signal have occurred between the successive internal reset signals to produce the reset signal so as to reset the recursive digital filter if N pulses of the serial clock input signal have not occurred between the successive internal reset signals. 10. The auto-resetting recursive digital filter circuitry of claim 9 wherein the counter is a Gray code counter. 11. The auto-resetting recursive digital filter circuitry of claim 9 wherein the input fault detection circuit includes a gate circuit having a first input coupled to the decoding circuit and a second input coupled to an external reset signal to allow external resetting of the recursive digital filter circuit. 12. The auto-resetting recursive digital filter circuitry of claim 9 wherein the corresponding edges of the successive pulses of the synchronization input signal are falling edges. 13. The auto-resetting recursive digital filter circuit of claim 1 wherein the input fault detection circuit detects the fault wherein the fault is associated with synchronization between the synchronization input signal and the serial clock input signal. 14. The auto-resetting recursive digital filter circuit of claim 1 wherein the fault is an input fault that would cause a persistent unstable condition in the recursive digital filter circuit. 15. The auto-resetting recursive digital filter circuit of claim 1 wherein the input fault detection operates to produce the reset signal if N pulses of the serial clock input signal fail to occur between successive pulses of the synchronization input signal. 16. A method of operating recursive digital filter circuitry to prevent a persistent unstable condition therein, the method comprising: applying a serial clock input signal, a synchronization input signal, and a serial data input signal to corresponding inputs of a three-wire serial interface circuit to produce a serial clock output signal, a synchronization output signal, and a parallel data output signal; applying the serial clock output signal, the synchronization output signal, and the parallel data output signal to corresponding inputs of a recursive digital filter circuit to produce a filtered over-sampled data output signal; monitoring the serial clock input signal and the synchronization input signal to detect a fault associated with one of the synchronization input signal and the serial clock input signal; and producing a reset signal in response to detection of the fault and coupling the reset signal to a reset input of the recursive digital filter circuit. 17. The method of claim 16 wherein the step of monitoring further comprises determining whether a ratio of the frequency of the serial clock input signal to the frequency of the synchronization input signal is equal to an oversampling ratio N between the serial clock input signal and the synchronization signal and producing the reset signal to reset the recursive digital filter circuit if the ratio is not equal to the oversampling ratio. 18. The method of claim 16 wherein the step of monitoring further comprises detecting a fault associated with synchronization between the synchronization input signal and the serial clock input signal. 19. The method of claim 16 including resetting the recursive digital filter circuit by resetting a register of the recursive digital filter circuit. 20. Auto-resetting recursive digital filter circuitry comprising: means for applying a serial clock input signal, a synchronization input signal, and a serial data input signal to corresponding inputs of a three-wire serial interface circuit to produce a serial clock output signal, a synchronization output signal, and a parallel data output signal; means for applying the serial clock output signal, the synchronization output signal, and the parallel data output signal to corresponding inputs of a recursive digital filter circuit to produce a filtered over-sampled data output signal; means for monitoring the serial clock input signal and the synchronization input signal to detect a fault associated with one of the synchronization input signal and the serial clock input signal; and means for producing a reset signal in response to detection of the fault and coupling the reset signal to a reset input of the recursive digital filter circuit to reset the recursive digital filter circuit if a ratio of the frequency of the serial clock input signal to the frequency of the synchronization input signal is not equal to an oversampling ratio between the serial clock signal and the synchronization input signal.
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