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Demotion-based arbitration 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-013/14
출원번호 UP-0821873 (2007-06-26)
등록번호 US-7685346 (2010-04-21)
발명자 / 주소
  • Teh, Chee Hak
  • Hunter, Arthur
출원인 / 주소
  • Intel Corporation
대리인 / 주소
    Trop, Pruner & Hu, P.C.
인용정보 피인용 횟수 : 18  인용 특허 : 13

초록

In one embodiment, the present invention includes a method for arbitrating requests from multiple agents based on an arbitration list to select an agent to receive an arbitration grant, determining whether the selected agent is associated with a grant counter that is at a value of zero, and if so dy

대표청구항

What is claimed is: 1. An apparatus comprising: a plurality of grant counters each associated with an agent of a system that is to request access to a resource, wherein each of the plurality of grant counters is to be decremented when the corresponding agent is granted access, and wherein a value o

이 특허에 인용된 특허 (13)

  1. MacCormack, Andrew, Arbiter for arbitrating between a plurality of requesters and method thereof.
  2. Gulick Dale E., Bus arbiter including aging factor counters to dynamically vary arbitration priority.
  3. Wille Ross M. (Sunnyvale CA) Carter Richard J. (Palo Alto CA), Distributed fair arbitration system using separate grant and request lines for providing access to data communication bu.
  4. Spencer David H. (Lebanon NJ) Becker Edward A. (Somerset NJ), Dynamic priority system for controlling the access of stations to a shared device.
  5. Arimilli Ravi Kumar ; Dodson John Steven ; Lewis Jerry Don ; Williams Derek Edward, Method and system for controlling access to a shared resource in a data processing system utilizing dynamically-determin.
  6. Lentz Derek J. (Los Gatos CA) Hagiwara Yasuaki (Santa Clara CA) Lau Te-Li (Palo Alto CA) Tang Cheng-Long (San Jose CA) Nguyen Le Trong (Monte Sereno CA), Microprocessor architecture with a switch network for data transfer between cache, memory port, and IOU.
  7. Beasley Michael W. (Owens Cross Roads AL), Minimum latency tie-breaking arbitration logic circuitry.
  8. Dale, Michele Z.; Latif, Farrukh A., Port manager controller for connecting various function modules.
  9. Gehman Judy M., Priority arbiter with shifting sequential priority scheme.
  10. O\Connell Anne (Galway IEX) Creedon Tadhg (Galway IEX) Smith Deidre A. (Kildare IEX), Programmable priority arbiter.
  11. Fukuyama,Toshihiro; Takai,Yuji; Kawamoto,Isao; Baba,Takahide; Murakami,Daisuke; Watanabe,Yoshiharu, Resource management device.
  12. Sarkar,Soujanna; Shurtz,Gregory R., Software programmable dynamic arbitration scheme.
  13. Thorsbakken,Lloyd E.; Byers,Larry L., System and method for managing input/output requests using a fairness throttle.

이 특허를 인용한 특허 (18)

  1. Lakshmanamurthy, Sridhar; Hunsaker, Mikal C.; Klinglesmith, Michael T.; Fanning, Blaise; Nair, Mohan K.; Murray, Joseph; Verma, Rohit R.; Lavelle, Gary J.; Adler, Robert P., Aggregating completion messages in a sideband interface.
  2. Okada, Masaki, Arbitration device, arbitration method, and electronic apparatus.
  3. Fujiwara, Makoto, Bus arbitration apparatus and bus arbitration method.
  4. Lakshmanamurthy, Sridhar; Adler, Robert P.; Hunsaker, Mikal C.; Klinglesmith, Michael T.; Fanning, Blaise; Tamari, Eran; Murray, Joseph; Verma, Rohit R., Common idle state, active state and credit management for an interface.
  5. Nimmala, Prashanth; Greiner, Robert J.; Looi, Lily P.; Vakharwala, Rupin H.; Song, Marcus W.; Beavens, James A.; Wood, Aimee D.; Tran, Jeff V., Integrating intellectual property (IP) blocks into a processor.
  6. Lakshmanamurthy, Sridhar; Hunsaker, Mikal C.; Klinglesmith, Michael T.; Fanning, Blaise; Tamari, Eran; Murray, Joseph; Wong, Kar Leong; Adler, Robert P., Issuing requests to a fabric.
  7. Lai, Siaw Kang, Providing a fine-grained arbitration system.
  8. Lai, Siaw Kang, Providing a fine-grained arbitration system.
  9. Adler, Robert P.; Tamari, Eran; Hunsaker, Mikal C.; Lakshmanamurthy, Sridhar; Klinglesmith, Michael T.; Fanning, Blaise, Providing a sideband message interface for system on a chip (SoC).
  10. Adler, Robert P.; Tamari, Eran; Hunsaker, Mikal C.; Lakshmanamurthy, Sridhar; Klinglesmith, Michael T.; Fanning, Blaise, Providing a sideband message interface for system on a chip (SoC).
  11. Lim, Kie Woon; Chew, E-Liang; Lee, Khee Wooi; Abramson, Darren L., Providing adaptive bandwidth allocation for a fixed priority arbiter.
  12. Lakshmanamurthy, Sridhar; Hunsaker, Mikal C.; Klinglesmith, Michael T.; Fanning, Blaise; Verma, Rohit R., Providing error handling support to legacy devices.
  13. Lakshmanamurthy, Sridhar; Hunsaker, Mikal C.; Klinglesmith, Michael T.; Fanning, Blaise; Verma, Rohit R., Providing error handling support to legacy devices.
  14. Lakshmanamurthy, Sridhar; Hunsaker, Mikal C.; Klinglesmith, Michael T.; Fanning, Blaise; Tamari, Eran; Murray, Joseph; Adler, Robert P., Providing multiple decode options for a system-on-chip (SoC) fabric.
  15. Lakshmanamurthy, Sridhar; Hunsaker, Mikal C.; Klinglesmith, Michael T.; Fanning, Blaise; Tamari, Eran; Murray, Joseph; Adler, Robert P., Providing multiple decode options for a system-on-chip (SoC) fabric.
  16. Lakshmanamurthy, Sridhar; Hunsaker, Mikal C.; Klinglesmith, Michael T.; Fanning, Blaise; Verma, Rohit R.; Adler, Robert P., Sending packets with expanded headers.
  17. Lakshmanamurthy, Sridhar; Hunsaker, Mikal C.; Klinglesmith, Michael T.; Fanning, Blaise; Verma, Rohit R.; Adler, Robert P., Sending packets with expanded headers.
  18. Lakshmanamurthy, Sridhar; Hunsaker, Mikal C.; Klinglesmith, Michael T.; Fanning, Blaise; Tamari, Eran; Murray, Joseph; Verma, Rohit R., Supporting multiple channels of a single interface.
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