IPC분류정보
국가/구분 |
United States(US) Patent
등록
|
국제특허분류(IPC7판) |
|
출원번호 |
UP-0743080
(2007-05-01)
|
등록번호 |
US-7693040
(2010-05-20)
|
발명자
/ 주소 |
- Bhugra, Harmeet
- Tezcan, Bertan
|
출원인 / 주소 |
- Integrated Device Technology, inc.
|
대리인 / 주소 |
|
인용정보 |
피인용 횟수 :
4 인용 특허 :
38 |
초록
▼
A baseband processor includes a processing switch for performing orthogonal frequency division multiplexing operations on data packets and routing the data packets in the baseband processor. Additionally, the baseband processor includes digital signal processors for performing symbol processing oper
A baseband processor includes a processing switch for performing orthogonal frequency division multiplexing operations on data packets and routing the data packets in the baseband processor. Additionally, the baseband processor includes digital signal processors for performing symbol processing operations on the data packets. The baseband processor is scalable such that digital signal processors may be added to, or removed from, the baseband processor. Further, the baseband processor is programmable such that the symbol processing operations may be distributed among the digital signal processors.
대표청구항
▼
What is claimed is: 1. A processing switch configured to receive a first baseband data packet comprising a header including a destination identifier for identifying a destination for the first baseband data packet and a data payload including a baseband input, generate a symbol data packet comprisi
What is claimed is: 1. A processing switch configured to receive a first baseband data packet comprising a header including a destination identifier for identifying a destination for the first baseband data packet and a data payload including a baseband input, generate a symbol data packet comprising data symbols by performing at least one orthogonal frequency division multiplexing operation on the baseband input, output the generated symbol data packet from terminals of the processing switch for processing the data symbols in the generated symbol data packet, receive a first set of channel data packets at terminals of the processing switch in response to outputting the generated symbol data packet, each channel data packet of the first set of channel data packets associated with at least one communication channel and comprising at least one processed data symbol, and output the first set of channel data packets. 2. The processing switch of claim 1 further configured to receive a second set of channel data packets each associated with at least one communication channel and comprising at least one data symbol, output the second set of channel data packets from terminals of the processing switch, receive a set of symbol data packets at terminals of the processing switch, each symbol data packet of the set of symbol data packets comprising at least one processed data symbol, generate a second baseband data packet comprising a baseband output by performing at least one orthogonal frequency division multiplexing operation on the set of symbol data packets, and output the second baseband data packet from the processing switch. 3. The processing switch of claim 2, wherein at least one of the first baseband data packet, the second baseband data packet, each channel data packet of the first set of channel data packets, each channel data packet of the second set of channel data packets, the generated symbol data packet, and each symbol data packet of the set of symbol data packets is formatted in a Serial RIO format. 4. The processing switch of claim 3, wherein at least one of the first baseband data packet, the second baseband data packet, each channel data packet of the first set of channel data packets, each channel data packet of the second set of channel data packets, the generated symbol data packet, and each symbol data packet of the set of symbol data packets is formatted in a Parallel RIO format. 5. The processing switch of claim 1, wherein each channel data packet of the first set of channel data packets comprises a header including a channel identifier identifying the channel associated with the channel data packet and a data payload including the at least one processed data symbol of the channel data packet, the processing switch further comprising a packet router for routing each channel data packet of the first set of channel data packets through the processing switch based on the channel identifier of the channel data packet. 6. The processing switch of claim 5, further comprising: a first processing block configured to convert the baseband input of the first baseband data packet to parallel data by performing at least one orthogonal frequency division multiplexing operation on the baseband input; a Fourier transform block coupled to the first processing block and configured to generate the data symbols of the generated symbol data packet by performing at least one Fourier transform on the parallel data; and a second processing block coupled to the Fourier transform block and configured to generate the symbol data packet based on the data symbols generated by the Fourier transform block. 7. A baseband processor comprising: a processing switch configured to receive a first baseband data packet comprising a header including a destination identifier for identifying a destination for the first baseband data packet and a data payload including a baseband input, the processing switch further configured to generate a symbol data packet comprising data symbols by performing at least one orthogonal frequency division multiplexing operation on the baseband input; and a plurality of digital signal processors coupled to the processing switch and configured to generate a first set of channel data packets each associated with at least one communication channel, each digital signal processor of the plurality of digital signal processors configured to generate a channel data packet of the first set of channel data packets by selecting at least one data symbol associated with a communication channel in the generated symbol data packet and performing at least one symbol processing operation on the at least one selected data symbol. 8. The baseband processor of claim 7, wherein performing the at least one symbol processing operation on the at least one selected data symbol comprises performing a synchronization operation. 9. The baseband processor of claim 7, wherein each digital signal processor of the plurality of digital signal processors is further configured to receive a channel data packet of a second set of channel data packets, each channel data packet of the second set of channel data packets associated with at least one communication channel and comprising at least one data symbol, and generate a symbol data packet of a set of symbol data packets by performing at least one symbol processing operation on the at least one data symbol in the received channel data packet, and the processing switch is further configured to generate a second baseband data packet comprising a baseband output by performing at least one orthogonal frequency division multiplexing operation on the set of symbol data packets. 10. The baseband processor of claim 7, further comprising a controller configured to program the plurality of digital signal processors. 11. The baseband processor of claim 10, wherein the controller is further configured to program the processing switch. 12. The baseband processor of claim 10, wherein the processing switch comprises a plurality of terminals, each digital signal processor of the plurality of digital signal processors is coupled to a corresponding terminal of the plurality of terminals, the plurality of terminals further comprises an available terminal not coupled to any digital signal processor, the processing switch is further configured to receive an additional digital signal processor at the available terminal, and the controller is further configured to program the additional digital signal processor. 13. The baseband processor of claim 7, further comprising: a switching fabric; a first interface coupled to the processing switch and the switching fabric, the first interface configured to receive a data packet and to route the data packet to the processing switch or the switching fabric based on an identifier of the data packet; and a second interface coupled to the processing switch and the switching fabric, the switching fabric further configured to receive a data packet from the first interface and to route the data packet to the second interface based on an identifier of the data packet. 14. The baseband processor of claim 7, further comprising a packet switch coupled to the plurality of digital signal processors and the second interface, the packet switch configured to receive the second set of channel data packets from the second interface and route each channel data packet of the second set of channel data packets to at least one digital signal processor of the plurality of digital signal processors. 15. The baseband processor of claim 7, wherein each of the first baseband data packet, the generated symbol data packet, and the first set of channel data packets is formatted in a Serial RIO format. 16. The baseband processor of claim 7, wherein each channel data packet of the first set of channel data packets comprises a header including a channel identifier identifying the channel associated with the channel data packet and a data payload including the at least one processed data symbol of the channel data packet, the processing switch further comprising a packet router for routing each channel data packet of the first set of channel data packets through the processing switch based on the channel identifier of the channel data packet. 17. The processing switch of claim 16, wherein the processing switch further comprises: a first processing block configured to convert the baseband input of the first baseband data packet to parallel data by performing at least one orthogonal frequency division multiplexing operation on the baseband input; a Fourier transform block coupled to the first processing block and configured to generate the data symbols of the generated symbol data packet by performing at least one Fourier transform on the parallel data; and a second processing block coupled to the Fourier transform block and configured to generate the symbol data packet based on the data symbols generated by the Fourier transform block. 18. A method of processing data in a wireless communication system, the method comprising: receiving a first baseband data packet comprising a header including a destination identifier for identifying a destination for the first baseband data packet and a data payload including a baseband input; generating a symbol data packet by performing at least one orthogonal frequency division multiplexing operation on the first baseband data packet, the generated symbol data packet comprising a plurality of data symbols each associated with a communication channel; selecting the data symbols associated with each communication channel in the generated symbol data packet; and generating a first set of channel data packets by performing at least one symbol processing operation on at least one data symbol of each communication channel selected from the generated symbol data packet to generate a corresponding channel data packet of the first set of channel data packets, each channel data packet of the first set of channel data packets associated with a communication channel. 19. The method of claim 18, wherein the first baseband data packet, the generated symbol data packet, and the first set of channel data packets are formatted in a Serial RIO format. 20. The method of claim 19, wherein selecting the data symbols associated with a communication channel in the generated symbol data packet is based on positions of the data symbols in the generated symbol data packet. 21. The method of claim 19, further comprising programming the digital signal processor to select the data symbols of the communication channel associated with the digital signal processor. 22. The method of claim 18, wherein selecting the data symbols associated with each communication channel in the generated symbol data packet comprises selecting the data symbols associated with a communication channel in the generated symbol data packet by a digital signal processor associated with the communication channel. 23. The method of claim 18, further comprising: receiving a second set of channel data packets each associated with at least one communication channel and comprising at least one data symbol; selecting data symbols in each channel data packet of the second set of channel data packets; generating a set of symbol data packets by performing at least one symbol processing operation on the selected data symbols of each channel data packet in the second set of channel data packets to generate a corresponding symbol data packet in the set of symbol data packets; and generating a second baseband data packet by performing at least one orthogonal frequency division multiplexing operation on the set of symbol data packets. 24. The method of claim 23, wherein each data packet of the second set of channel data packets comprises an identifier and selecting the data symbols of each channel data packet in the second set of channel data packets is based on the identifier of the channel data packet. 25. The method of claim 23, wherein selecting the data symbols in each channel data packet of the second set of channel data packets comprises selecting the data symbols of a channel data packet of the second set of channel data packets by a digital signal processor associated with the communication channel of the channel data packet. 26. The method of claim 18, wherein each channel data packet of the first set of channel data packets comprises a header including a channel identifier identifying the channel associated with the channel data packet and a data payload including the at least one processed data symbol of the channel data packet, the method further comprising routing each channel data packet of the first set of channel data packets through a processing switch based on the channel identifier of the channel data packet. 27. The method of claim 26, further comprising: converting the baseband input of the first baseband data packet to parallel data by performing at least one orthogonal frequency division multiplexing operation on the baseband input; and generating the data symbols of the generated symbol data packet by performing at least one Fourier transform on the parallel data.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.