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Programmable logic device with specialized functional block 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-007/38
출원번호 UP-0746448 (2003-12-24)
등록번호 US-7698358 (2010-05-20)
발명자 / 주소
  • Langhammer, Martin
  • Zheng, Leon
  • Hwang, Chiao Kai
  • Starr, Gregory
출원인 / 주소
  • Altera Corporation
대리인 / 주소
    Ropes & Gray LLP
인용정보 피인용 횟수 : 7  인용 특허 : 37

초록

In a programmable logic device having a specialized functional block incorporating multipliers and adders, multiplication operations that do not fit neatly into the available multipliers are performed partially in the multipliers of the specialized functional block and partially in multipliers confi

대표청구항

What is claimed is: 1. A specialized functional block for use in a programmable logic device, said specialized functional block comprising: a plurality of block inputs; a plurality of dedicated multiplier circuits having multiplier inputs connected to said block inputs, and having multiplier output

이 특허에 인용된 특허 (37)

  1. Rajski Janusz ; Tyszer Jerzy,PLX, Arithmetic built-in self test of multiple scan-based integrated circuits.
  2. Yu, Robert K.; Padmanabhan, Satish; Srivatsa, Chakra R.; Shah, Shailesh I., Circuit and method for multiplying and accumulating the sum of two products in a single cycle.
  3. Jiang Shao-Kun ; Wong Roney S. ; Peter-Song Seungyoon, Computational structure having multiple stages wherein each stage includes a pair of adders and a multiplexing circuit capable of operating in parallel.
  4. Freeman ; deceased Ross H. (late of San Jose CA by Dennis Hersey ; executor), Configurable electrical circuit having configurable logic elements and configurable interconnects.
  5. Bhandal, Amarjit Singh; Balmer, Keith; Hoyle, David; Guttag, Karl M.; Hussain, Zahid, Data processor with flexible multiply unit.
  6. Langhammer, Martin; Starr, Gregory; Hwang, Chiao Kai, Devices and methods with programmable logic and digital signal processing regions.
  7. New Bernard J., Field programmable gate array with distributed gate-array functionality.
  8. Yano Naoka,JPX ; Tamura Naoyuki,JPX, High-efficiency multiplier and multiplying method.
  9. Krishna Rangasayee, Integrated circuit incorporating a programmable cross-bar switch.
  10. Tavana Danesh ; Yee Wilson K. ; Trimberger Stephen M., Integrated circuit with field programmable and application specific logic areas.
  11. John Anthony Schadt, Integrated circuit with standard cell logic and spare gates.
  12. Tony Ngai ; Bruce Pedersen ; Sergey Shumarayev ; James Schleicher ; Wei-Jen Huang ; Michael Hutton ; Victor Maruri ; Rakesh Patel ; Peter J. Kazarian ; Andrew Leaver ; David W. Mendel ; Ji, Interconnection and input/output resources for programmable logic integrated circuit devices.
  13. Steele Randy C. (Southlake TX), Logic block for programmable logic devices.
  14. Beiu Valeriu, Logic gate having reduced power dissipation and method of operation thereof.
  15. Cliff Richard G. ; Heile Francis B. ; Huang Joseph ; Mendel David W. ; Pedersen Bruce B. ; Sung Chiakang ; Wang Bonnie I., Logic region resources for programmable logic devices.
  16. New Bernard J. (Los Gatos CA), Logic structure and circuit for fast carry.
  17. Baeg Sanghyeon, Low cost emulation scheme implemented via clock control using JTAG controller in a scan environment.
  18. De Vivek K. ; Ye Yibin, Method and apparatus for reducing standby leakage current using a transistor stack effect.
  19. Kojima Hirotsugu ; Shridhar Avadhani, Method and apparatus for reducing the power consumption in a programmable digital signal processor.
  20. Schultz David P. ; Young Steven P. ; Hung Lawrence C., Method and structure for reading, modifying and writing selected configuration memory cells of an FPGA.
  21. Jenkins ; IV. Jesse H. ; Seltzer Jeffrey H. ; Curd Derek R., Method of minimizing power use in programmable logic devices.
  22. Telikepalli Anil L. N., Multiplier circuit design for a programmable logic device.
  23. New Bernard J., Multiplier fabric for use in field programmable gate arrays.
  24. Chan Andrew K. (Palo Alto CA) Birkner John M. (Portola Valley CA) Chua Hua-Thye (Los Altos Hills CA), Programmable application specific integrated circuit and logic cell therefor.
  25. Oswald William A. (Allentown PA) Singh Satwant (Macungie PA), Programmable function unit as parallel multiplier cell.
  26. Cliff Richard G. (Milpitas CA) Reddy Srinivas T. (Santa Clara CA) Raman Rina (Fremont CA) Cope L. Todd (San Jose CA) Huang Joseph (San Jose CA) Pedersen Bruce B. (San Jose CA), Programmable logic array integrated circuit devices.
  27. Rangasayee Krishna ; Bielby Robert N., Programmable logic device architecture incorporating a dedicated cross-bar switch.
  28. Jefferson David E. ; McClintock Cameron ; Schleicher James ; Lee Andy L. ; Mejia Manuel ; Pedersen Bruce B. ; Lane Christopher F. ; Cliff Richard G. ; Reddy Srinivas T., Programmable logic device architecture with super-regions having logic regions and a memory region.
  29. Lane Christopher F. ; Reddy Srinivas T. ; Cliff Richard G. ; Zaveri Ketan H. ; Pedersen Bruce B. ; Veenstra Kerry, Programmable logic device circuitry for improving multiplier speed and/or efficiency.
  30. Patel Rakesh H. (Santa Clara CA) Turner John E. (Santa Cruz CA) Wong Myron W. (San Jose CA), Programmable logic device having multiplexers and demultiplexers randomly connected to global conductors for interconnec.
  31. Langhammer, Martin; Hwang, Chiao Kai; Starr, Gregory, Programmable logic device including multipliers and configurations thereof to reduce resource utilization.
  32. Wong Sau-Ching (Hillsborough CA) So Hock-Chuen (Milpitas CA) Kopec ; Jr. Stanley J. (San Jose CA) Hartmann Robert F. (San Jose CA), Programmable logic device with array blocks connected via programmable interconnect.
  33. Costello John C. (San Jose CA) Patel Rakesh H. (Santa Clara CA), Programmable logic device with logic block outputs coupled to adjacent logic block output multiplexers.
  34. Sharpe-Geisler Bradley A. ; Moyer Bryon I., Programmable logic device with multi-level power control.
  35. Langhammer, Martin; Prasad, Nitin, Programmable logic devices with function-specific blocks.
  36. Steele Randy C. (Scottsdale AZ) Raad Safoin A. (Scottsdale AZ), Programmable summing functions for programmable logic devices.
  37. Mori Shojiro (Kawasaki JPX), Transfer circuit for operation test of LSI systems.

이 특허를 인용한 특허 (7)

  1. Langhammer, Martin, Digital signal processing circuitry with redundancy and ability to support larger multipliers.
  2. Langhammer, Martin; Lin, Yi-Wen; Streicher, Keone, Digital signal processing circuitry with redundancy and bidirectional data paths.
  3. Langhammer, Martin; Tharmalingam, Kumara, Large multiplier for programmable logic device.
  4. Langhammer, Martin; Tharmalingam, Kumara, Large multiplier for programmable logic device.
  5. Streicher, Keone; Langhammer, Martin; Lin, Yi-Wen; Leung, Wai-Bor; Lewis, David; Mauer, Volker; Lui, Henry Y.; Demirsoy, Suleyman Sirri; Yi, Hyun, Modular digital signal processing circuitry with optionally usable, dedicated connections between modules of the circuitry.
  6. Streicher, Keone; Langhammer, Martin; Lin, Yi-Wen; Leung, Wai-Bor; Lewis, David; Mauer, Volker; Lui, Henry Y.; Demirsoy, Suleyman Sirri; Yi, Hyun, Modular digital signal processing circuitry with optionally usable, dedicated connections between modules of the circuitry.
  7. Streicher, Keone; Langhammer, Martin; Lin, Yi-Wen; Leung, Wai-Bor; Lewis, David; Mauer, Volker; Lui, Henry Y.; Demirsoy, Suleyman Sirri; Yi, Hyun, Modular digital signal processing circuitry with optionally usable, dedicated connections between modules of the circuitry.
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