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A semiconductor integrated circuit includes a reconfigurable circuit including a plurality of computing units interconnected in a reconfigurable manner, a processing circuit including at least one of a fixed logic circuit configured to perform predetermined processing and a parameter-defined special

A semiconductor integrated circuit includes a reconfigurable circuit including a plurality of computing units interconnected in a reconfigurable manner, a processing circuit including at least one of a fixed logic circuit configured to perform predetermined processing and a parameter-defined special-purpose hardware unit configured to change processing specifications according to parameter settings, a network having reconfigurable connections and coupled to the reconfigurable circuit and to the processing circuit, and at least two interfaces each coupled to the network to provide external coupling for the network.

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What is claimed is: 1. A semiconductor integrated circuit, comprising a plurality of processing sets, each including: a reconfigurable circuit including a plurality of computing units interconnected in a reconfigurable manner a processing circuit being either a fixed logic circuit configured to per

What is claimed is: 1. A semiconductor integrated circuit, comprising a plurality of processing sets, each including: a reconfigurable circuit including a plurality of computing units interconnected in a reconfigurable manner a processing circuit being either a fixed logic circuit configured to perform predetermined processing or a parameter-defined special-purpose hardware unit configured to change processing specifications according to parameter settings; a network having reconfigurable connections and coupled to said reconfigurable circuit and to said processing circuit; and a first interface and a second interface each coupled to said network to provide external coupling for said network, wherein said networks of said plurality of processing sets are connected in series through said interfaces, and the networks situated at opposite ends of said series are connectable to an exterior of said semiconductor integrated circuit through said interfaces, wherein each of the networks is configured such that selected ones of the signal lines of one network corresponding to a given one of the processing sets are coupled, through one of the first interface and the second interface, to inputs of the reconfigurable circuit and the processing circuit in another one of the processing sets, the number of the selected ones of the signal lines being smaller than the number of the signal lines of the one network, wherein the network includes: a first set of one or more signal lines coupled to the reconfigurable circuit and the processing circuit and further coupled to the first interface, the first set of one or more signal lines carrying one or more signals received from the first interface; a second set of one or more signal lines coupled to the reconfigurable circuit and the processing circuit and further coupled to the second interface, the second set of one or more signal lines carrying one or more signals received from the second interface; a third set of one or more signal lines coupled to the reconfigurable circuit and the processing circuit, the third set of one or more signal lines carrying one or more signals between the reconfigurable circuit and the processing circuit; at least one selector configured to provide the reconfigurable connections in the network; a first signal-line selector configured to select a first predetermined number of signal lines from the first and third sets of one or more signal lines, and only the first predetermined number of signal lines selected by the first signal-line selector being coupled to the second interface for signal transmission for the first and third sets of one or more signal lines; and a second signal-line selector configured to select a second predetermined number of signal lines from the second and third sets of one or more signal lines, and only the second predetermined number of signal lines selected by the second signal-line selector being coupled to the first interface for signal transmission for the second and third sets of one or more signal lines. 2. The semiconductor integrated circuit as claimed in claim 1, further comprising: a bus coupled to said reconfigurable circuit and said processing circuit; and a processor coupled to said bus. 3. The semiconductor integrated circuit as claimed in claim 2, further comprising a control circuit configured to control the connections of said network, wherein said control circuit is configured to set the connections of said network in response to instruction supplied from said processor. 4. The semiconductor integrated circuit as claimed in claim 2, wherein said reconfigurable circuit is configured to define what computations are performed by said plurality of computing units in response to setting data supplied from said processor. 5. The semiconductor integrated circuit as claimed in claim 2, further comprising a system interface configured to couple said processor to an external system. 6. The semiconductor integrated circuit as claimed in claim 1, wherein said network includes a crossbar configured to interconnect between said reconfigurable circuit and said processing circuit. 7. The semiconductor integrated circuit as claimed in claim 1, wherein said parameter-defined special-purpose hardware unit includes: a special-purpose hardware configured to perform predetermined processing; and a setting register configured to store therein data that defines operation and processing specifications of said special-purpose hardware. 8. The semiconductor integrated circuit as claimed in claim 1, wherein said processing circuit further includes an interface configured to exchange a signal with an exterior of said semiconductor integrated circuit. 9. The semiconductor integrated circuit as claimed in claim 1 wherein outputs of the reconfigurable circuit and the processing circuit of a given set are separated by the first or second interface from outputs of the reconfigurable circuit and the processing circuit of another set.