Porous semiconductor-based evaporator having porous and non-porous regions, the porous regions having through-holes
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H01L-047/00
H01L-023/06
출원번호
UP-0530107
(2006-09-08)
등록번호
US-7705342
(2010-05-20)
발명자
/ 주소
Henderson, H. Thurman
Shuja, Ahmed
Parimi, Srinivas
Gerner, Frank M.
Medis, Praveen
출원인 / 주소
University of Cincinnati
대리인 / 주소
Perkins Coie LLP
인용정보
피인용 횟수 :
2인용 특허 :
37
초록▼
The present invention is a MEMS-based two-phase LHP (loop heat pipe) and CPL (capillary pumped loop) using semiconductor grade silicon and microlithographic/anisotrophic etching techniques to achieve a planar configuration. The principal working material is silicon (and compatible borosilicate glass
The present invention is a MEMS-based two-phase LHP (loop heat pipe) and CPL (capillary pumped loop) using semiconductor grade silicon and microlithographic/anisotrophic etching techniques to achieve a planar configuration. The principal working material is silicon (and compatible borosilicate glass where necessary), particularly compatible with the cooling needs for electronic and computer chips and package cooling. The microloop heat pipes (μLHP™) utilize cutting edge microfabrication techniques. The device has no pump or moving parts, and is capable of moving heat at high power densities, using revolutionary coherent porous silicon (CPS) wicks. The CPS wicks minimize packaging thermal mismatch stress and improves strength-to-weight ratio. Also burst-through pressures can be controlled as the diameter of the coherent pores can be controlled on a sub-micron scale. The two phase planar operation provides extremely low specific thermal resistance (20-60 W/cm2). The operation is dependent upon a unique micropatterened CPS wick which contains up to millions per square centimeter of stacked uniform micro-through-capillaries in semiconductor-grade silicon, which serve as the capillary “engine,” as opposed to the stochastic distribution of pores in the typical heat pipe wick. As with all heat pipes, cooling occurs by virtue of the extraction of heat by the latent heat of phase change of the operating fluid into vapor. In the cooling of a laptop computer processor the device could be attached to the processor during laptop assembly. Consistent with efforts to miniaturize electronics components, the current invention can be directly integrated with a unpackaged chip. For applications requiring larger cooling surface areas, the planar evaporators can be spread out in a matrix and integrally connected through properly sized manifold systems.
대표청구항▼
What is claimed is: 1. A porous structure based evaporator, the evaporator comprising: a first material layer, the first material layer having porous regions at a first set of predetermined areas and non-porous regions at a second set of predetermined areas, the porous regions comprising a pluralit
What is claimed is: 1. A porous structure based evaporator, the evaporator comprising: a first material layer, the first material layer having porous regions at a first set of predetermined areas and non-porous regions at a second set of predetermined areas, the porous regions comprising a plurality of through-holes between a first surface of the first material layer and a second surface of the first material layer; and a cap structure coupled to the first material layer to form an enclosure over the first surface of the first material layer, the enclosure formed from contact of peripheral regions of the cap structure with the first material layer at a first non-porous region of the second set of predetermined areas, wherein, the cap is formed to contact the first surface of the first material layer at a second non-porous region of the second set of predetermined areas. 2. The evaporator of claim 1, wherein the first layer material comprises metallic material. 3. The evaporator of claim 1, further comprising, a chamber coupled to the second surface of the first layer, the chamber having a recessed region adjacent to the second surface of the first layer. 4. The evaporator of claim 3, wherein the chamber is formed with one or more of a liquid inlet port and a vapor outlet port. 5. A porous semiconductor structure based evaporator, the evaporator comprising: a first layer of semiconductor-based material, the first layer having porous regions at a first set of predetermined areas and non-porous regions at a second set of predetermined areas, the porous regions comprising a plurality of through-holes between a first surface of the first layer and a second surface of the first layer; and a cap structure coupled td the first layer to form an enclosure over the first surface of the first layer, the enclosure formed from contact of peripheral regions of the cap structure with the first layer at a first non-porous region of the second set of predetermined areas, wherein the cap structure is formed to contact the first surface of the first layer at a second non-porous region of the second set of predetermined areas. 6. The evaporator of claim 5, further comprising, a chamber coupled to the second surface of the first layer, the chamber having a recessed region adjacent to the second surface of the first layer. 7. The evaporator of claim 6, wherein the chamber is formed with one or more of a liquid inlet port and a vapor outlet port. 8. The evaporator of claim 6, wherein one or more of the cap structure and the chamber is formed by ultrasonic impact grinding. 9. The evaporator of claim 7, wherein liquid is disposed in the recessed region of the chamber to be substantially in contact with at least a portion of the porous regions at the first set of predetermined areas, the liquid to be supplied via the at least one liquid inlet port. 10. The evaporator of claim 6, wherein the chamber is comprised substantially of, one or more of, glass, silicon, and ceramics. 11. The evaporator of claim 5, wherein an exterior surface of the cap structure is suited to be thermally coupled to a heat source. 12. The evaporator of claim 6, further comprising, a second layer comprised substantially of fibrous material coupled to the second surface of the first layer; wherein the second layer is disposed in the recessed region of the chamber. 13. The evaporator of claim 12, wherein the second layer comprises a plurality of layers of fibrous material with varying pore sizes. 14. The evaporator of claim 12, wherein the fibrous material is comprised substantially of one or more of, silicon dioxide fiber, glass, and asbestos fiber. 15. The evaporator of claim 5, wherein the first layer is coupled to the cap structure via wafer bonding at the peripheral regions of the top cap and the protruding structures of the top cap to the first layer at the non-porous region of the second set of predetermined areas. 16. The evaporator of claim 15, wherein the wafer bonding is achieved via indium-gold solid-liquid inter-diffusion. 17. The evaporator of claim 5, wherein the cap structure is formed with at least one vapor outlet port. 18. The evaporator of claim 5, wherein the cap structure is comprised substantially of, thermally conductive material. 19. The evaporator of claim 18, wherein the cap structure comprises substantially of one or more of, silicon and CMOS-grade silicon. 20. The evaporator of claim 5, wherein the first layer comprises substantially of, crystalline semiconductor. 21. The evaporator of claim 20, wherein the crystalline semiconductor is [100]-type crystalline semiconductor. 22. The evaporator of claim 21, wherein the crystalline semiconductor is silicon. 23. The evaporator of claim 21, wherein the porous region comprises coherent silicon pores that are substantially uniform in distribution and dimension to form the plurality of through-holes. 24. The evaporator of claim 23, wherein the coherent silicon pores have a substantially high length to diameter aspect ratio. 25. The evaporator of claim 23, wherein the coherent silicon pores have a length to diameter aspect ratio of 60 to 200.
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