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Methods and structures for monolithically integrating monocrystalline silicon and monocrystalline non-silicon materials and devices are provided. In one structure, a monolithically integrated semiconductor device structure comprises a silicon substrate and a first monocrystalline semiconductor layer

Methods and structures for monolithically integrating monocrystalline silicon and monocrystalline non-silicon materials and devices are provided. In one structure, a monolithically integrated semiconductor device structure comprises a silicon substrate and a first monocrystalline semiconductor layer disposed over the silicon substrate, wherein the first monocrystalline semiconductor layer has a lattice constant different from a lattice constant of relaxed silicon. The structure further includes an insulating layer disposed over the first monocrystalline semiconductor layer in a first region and a monocrystalline silicon layer disposed over the insulating layer in the first region. The structure includes at least one silicon-based photodetector comprising an active region including at least a portion of the monocrystalline silicon layer. The structure also includes a second monocrystalline semiconductor layer disposed over at least a portion of the first monocrystalline semiconductor layer in a second region and absent from the first region, wherein the second monocrystalline semiconductor layer has a lattice constant different from the lattice constant of relaxed silicon. The structure includes at least one non-silicon photodetector comprising an active region including at least a portion of the second monocrystalline semiconductor layer.

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What is claimed is: 1. A monolithically integrated semiconductor device structure comprising: a silicon substrate; a first monocrystalline semiconductor layer disposed over the silicon substrate, wherein the first monocrystalline semiconductor layer has a lattice constant different from a lattice c

What is claimed is: 1. A monolithically integrated semiconductor device structure comprising: a silicon substrate; a first monocrystalline semiconductor layer disposed over the silicon substrate, wherein the first monocrystalline semiconductor layer has a lattice constant different from a lattice constant of relaxed silicon; an insulating layer disposed over the first monocrystalline semiconductor layer in a first region; a monocrystalline silicon layer disposed over the insulating layer in the first region; at least one silicon-based photodetector comprising an active region including at least a portion of the monocrystalline silicon layer; a second monocrystalline semiconductor layer disposed over at least a portion of the first monocrystalline semiconductor layer in a second region and absent from the first region, wherein the second monocrystalline semiconductor layer has a lattice constant different from the lattice constant of relaxed silicon; and at least one non-silicon photodetector comprising an active region including at least a portion of the second monocrystalline semiconductor layer. 2. The semiconductor structure of claim 1, wherein the second monocrystalline semiconductor layer has a composition different than that of the first monocrystalline layer. 3. The semiconductor structure of claim 1, further comprising: at least one silicon-based electronic device comprising an element including at least a portion of the monocrystalline silicon layer. 4. The semiconductor structure of claim 3, wherein the at least one silicon-based electronic device comprises a metal oxide semiconductor field-effect transistor. 5. The semiconductor structure of claim 3, further comprising: an electrical interconnect coupling the at least one silicon-based electronic device with the at least one silicon-based photodetector and the at least one non-silicon photodetector, so that the at least one silicon-based electronic device is configured to receive photodetection signals from the at least one silicon-based photodetector and the at least one non-silicon photodetector. 6. The semiconductor structure of claim 1, wherein the second monocrystalline semiconductor layer is disposed in contact with the at least a portion of the first monocrystalline semiconductor layer. 7. The semiconductor structure of claim 1, wherein a top surface of the second monocrystalline semiconductor layer is substantially coplanar with a top surface of the monocrystalline silicon layer. 8. The semiconductor structure of claim 1, wherein the second monocrystalline semiconductor layer comprises a III-V semiconductor layer. 9. The semiconductor structure of claim 8, further comprising a silicon layer disposed over the III-V semiconductor layer. 10. The semiconductor structure of claim 9, wherein the silicon layer is disposed in contact with the III-V semiconductor layer. 11. The semiconductor structure of claim 1, wherein the monocrystalline silicon layer comprises a relaxed silicon layer. 12. The semiconductor structure of claim 1, wherein the monocrystalline silicon layer comprises a strained silicon layer. 13. The semiconductor structure of claim 1, further comprising a second insulating layer disposed over the silicon substrate and under the first monocrystalline semiconductor layer. 14. The semiconductor structure of claim 1, wherein the first monocrystalline semiconductor layer comprises at least two monocrystalline semiconductor layers disposed over each other and having lattice constants different from each other and different from the lattice constant of relaxed silicon. 15. The semiconductor structure of claim 14, wherein the at least two monocrystalline semiconductor layers comprise a germanium layer and an InP layer. 16. The semiconductor structure of claim 14, wherein the at least two monocrystalline semiconductor layers comprise a germanium layer and a GaN layer. 17. The semiconductor structure of claim 14, wherein the at least two monocrystalline semiconductor layers comprise a GaAs layer and an InP layer. 18. The semiconductor structure of claim 14, wherein the at least two mono-crystalline semiconductor layers comprise a GaAs layer and a GaN layer. 19. The semiconductor structure of claim 1, wherein the first monocrystalline semiconductor layer comprises a germanium layer. 20. The semiconductor structure of claim 19, wherein the first monocrystalline semiconductor layer further comprises a silicon-germanium graded layer disposed under the germanium layer. 21. The semiconductor structure of claim 19, further comprising a second insulating layer disposed over the silicon substrate and under the germanium layer. 22. The semiconductor structure of claim 21, wherein the germanium layer is disposed in contact with the second insulating layer. 23. The semiconductor structure of claim 1, wherein the first monocrystalline semiconductor layer comprises a silicon-germanium layer. 24. The semiconductor structure of claim 23, wherein the first monocrystalline semiconductor layer further comprises a silicon-germanium graded layer disposed under the silicon-germanium layer. 25. The semiconductor structure of claim 23, further comprising a second insulating layer disposed over the silicon substrate and under the silicon-germanium layer. 26. The semiconductor structure of claim 25, wherein the silicon-germanium layer is disposed in contact with the second insulating layer. 27. The semiconductor structure of claim 1, wherein the first monocrystalline semiconductor layer comprises a III-V semiconductor layer. 28. The semiconductor structure of claim 27, wherein the III-V semiconductor layer comprises a GaN layer. 29. The semiconductor structure of claim 27, wherein the III-V semiconductor layer comprises a GaAs layer. 30. The semiconductor structure of claim 27, wherein the first monocrystalline semiconductor layer further comprises a germanium layer disposed under the III-V semiconductor layer. 31. The semiconductor structure of claim 27, wherein the first monocrystalline semiconductor layer further comprises a silicon-germanium layer disposed under the III-V semiconductor layer. 32. The semiconductor structure of claim 27, wherein the first monocrystalline semiconductor layer further comprises a silicon-germanium graded layer disposed under the III-V semiconductor layer. 33. The semiconductor structure of claim 1, wherein the silicon substrate has a diameter of at least 150 millimeters. 34. The semiconductor structure of claim 1, wherein the silicon substrate has a diameter of at least 200 millimeters. 35. A method of forming a monolithically integrated semiconductor device structure, the method comprising: providing a silicon substrate; forming a first monocrystalline semiconductor layer over the silicon substrate, wherein the first monocrystalline semiconductor layer has a lattice constant different from a lattice constant of relaxed silicon; forming an insulating layer over the first monocrystalline semiconductor layer in a first region; forming a monocrystalline silicon layer over the insulating layer in the first region; forming at least one silicon-based photodetector comprising an active region including at least a portion of the monocrystalline silicon layer; forming a second monocrystalline semiconductor layer over at least a portion of the first monocrystalline semiconductor layer in a second region and absent from the first region, wherein the second monocrystalline semiconductor layer has a lattice constant different from the lattice constant of relaxed silicon; and forming at least one non-silicon photodetector comprising an active region including at least a portion of the second monocrystalline semiconductor layer. 36. A monolithically integrated semiconductor device structure comprising: a silicon substrate; a first monocrystalline semiconductor layer disposed over the silicon substrate, wherein the first monocrystalline semiconductor layer has a lattice constant different from a lattice constant of relaxed silicon; a monocrystalline silicon layer disposed over the first monocrystalline semiconductor layer in the first region; at least one silicon-based photodetector comprising an active region including at least a portion of the monocrystalline silicon layer; a second monocrystalline semiconductor layer disposed on at least a portion of the first monocrystalline semiconductor layer in a second region and absent from the first region, wherein the second monocrystalline semiconductor layer has a lattice constant different from the lattice constant of relaxed silicon; and at least one non-silicon photodetector comprising an active region including at least a portion of the second monocrystalline semiconductor layer. 37. The semiconductor structure of claim 36, further comprising a layer in the first region disposed between the monocrystalline silicon layer and the first monocrystalline semiconductor layer. 38. The semiconductor structure of claim 37, wherein the layer in the first region disposed between the monocrystalline silicon layer and the first monocrystalline semiconductor layer is a non-insulating layer. 39. The semiconductor structure of claim 37, wherein the layer in the first region disposed between the monocrystalline silicon layer and the first monocrystalline semiconductor layer is an insulating layer. 40. The semiconductor structure of claim 36, wherein at least a portion of the second monocrystalline semiconductor layer has a composition different than a composition of the first monocrystalline layer.