초록 ▼

Built-in self test techniques for testing circuit blocks on integrated circuits are provided. A BIST controller is provided on-chip to test two or more circuit blocks. High routing congestion is avoided by loading test data into the circuit blocks through scan chain segments that run continuously al

Built-in self test techniques for testing circuit blocks on integrated circuits are provided. A BIST controller is provided on-chip to test two or more circuit blocks. High routing congestion is avoided by loading test data into the circuit blocks through scan chain segments that run continuously along the inputs and outputs of the circuit blocks. The BIST controller takes control of the scan chain segments during test and has the ability to partition the scan chains at specified intervals.

대표청구항 ▼

What is claimed is: 1. A method for testing a plurality of on-chip memory blocks on an integrated circuit, the method comprising: configuring a plurality of data selection circuits with a control signal, wherein a first state of the control signal configures the plurality of data selection circuits

What is claimed is: 1. A method for testing a plurality of on-chip memory blocks on an integrated circuit, the method comprising: configuring a plurality of data selection circuits with a control signal, wherein a first state of the control signal configures the plurality of data selection circuits for transferring built-in self test (BIST) data and address values from a single BIST controller serially to input scan chain segments associated with a plurality of on-chip memory blocks; wherein a second state of the control signal configures the plurality of data selection circuits for transferring the BIST data and the address values from the single BIST controller in parallel to the input scan chain segments associated with the plurality of on-chip memory blocks; loading the BIST data from the input scan chain segments into memory cells in the plurality of on-chip memory blocks; reading output BIST data from the memory cells; loading the output BIST data read from the memory cells into output scan chain segments associated with the plurality of on-chip memory blocks; transferring the output BIST data from the output scan chain segments to comparators; performing OR logic functions on the output signals of the comparators and output signals of registers using logic gates; and transferring output signals of the logic gates to inputs of the registers. 2. The method as defined in claim 1 wherein the integrated circuit is a mask programmable logic device. 3. The method as defined in claim 1 wherein the integrated circuit is an application specific integrated circuit. 4. The method as defined in claim 1 further comprising: comparing the output BIST data to expected data using a set of comparators coupled to the output scan chain segments. 5. The method as defined in claim 1 further comprising: comparing a first bit of the output BIST data to a second bit of the output BIST data using a first comparator; and comparing the first bit of the output BIST data to a third bit of the output BIST data using a second comparator. 6. The method as defined in claim 1 further comprising: transferring the output BIST data from the output scan chain segments to comparators; generating a BIST mask signal; and blocking output signals of the comparators in response to the BIST mask signal using logic gates. 7. The method as defined in claim 1 wherein the data selection circuits comprise multiplexers. 8. The method as defined in claim 1, wherein loading the BIST data from the input scan chain segments into the memory cells uses the address values. 9. The method as defined in claim 1, wherein the input scan chain segments are the output scan chain segments. 10. An integrated circuit comprising a system for testing multiple on-chip circuit blocks, the integrated circuit comprising: a built-in self-test (BIST) controller that generates input BIST data; a plurality of circuit blocks; input scan chain segments associated with the plurality of circuit blocks that receive input BIST data from the BIST controller and load the input BIST data into the circuit blocks; output scan chain segments associated with the plurality of circuit blocks that receive output BIST data read from the plurality of circuit blocks; a plurality of comparators, each having a first input coupled to an output of an output scan chain segment and a second input coupled to receive expected data; a plurality of OR gates coupled to receive output signals of the comparators; and a plurality of registers coupled between outputs and inputs of the OR gates. 11. The integrated circuit defined in claim 10 further comprising: a plurality of multiplexers coupled between outputs of the BIST controller and inputs of the input scan chain segments. 12. The integrated circuit defined in claim 10 further comprising: a plurality of AND gates that are coupled to outputs of the comparators, wherein the plurality of OR gates are coupled to outputs of the AND gates, and wherein the plurality of registers are coupled between outputs and inputs of the OR gates. 13. The integrated circuit defined in claim 10 wherein the output scan chain segments are coupled together in serial to an input of the BIST controller. 14. The integrated circuit defined in claim 10 further comprising: a plurality of multiplexers coupled between the input scan chain segments so that test data can be serially shifted into the input scan chain segments. 15. The integrated circuit defined in claim 10 wherein the integrated circuit is a mask programmable logic device, and wherein the input scan chains are operable to test additional circuit blocks on the integrated circuit. 16. The integrated circuit defined in claim 10 wherein the plurality of circuit blocks are memory blocks.