Integrated electromagnetic interference filters and feedthroughs
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H05K-007/02
H05K-007/06
H05K-007/08
H05K-007/10
출원번호
UP-0632138
(2003-07-31)
등록번호
US-7719854
(2010-06-10)
발명자
/ 주소
Youker, Nick A.
Swanson, Lawrence D.
Hansen, John E.
Linder, William J.
출원인 / 주소
Cardiac Pacemakers, Inc.
대리인 / 주소
Schwegman, Lundberg & Woessner, P.A.
인용정보
피인용 횟수 :
30인용 특허 :
41
초록▼
An assembly integrating commercially available capacitors into filtered feedthroughs. A feedthrough assembly comprises a plurality of Input/Output (I/O) conductors, wherein the I/O conductors pass through a hermetic seal such that a first end of the I/O conductors reside on a non-hermetic side of th
An assembly integrating commercially available capacitors into filtered feedthroughs. A feedthrough assembly comprises a plurality of Input/Output (I/O) conductors, wherein the I/O conductors pass through a hermetic seal such that a first end of the I/O conductors reside on a non-hermetic side of the hermetic seal and a second end of the I/O conductors reside on a hermetic side of the hermetic seal, a printed circuit interconnect substrate residing on the hermetic side of the hermetic seal, and a plurality of ceramic chip capacitors mounted on the printed circuit interconnect substrate, wherein a first end of each capacitor is connected via the interconnect to the second end of an I/O conductor and a second end of each capacitor is connected via the interconnect to a constant voltage level.
대표청구항▼
What is claimed is: 1. An apparatus comprising: one or more Input/Output (I/O) conductors, wherein the I/O conductors pass through a hermetic seal such that a first end of the I/O conductors resides on a non-hermetic side of the hermetic seal and a second end of the I/O conductors resides on a herm
What is claimed is: 1. An apparatus comprising: one or more Input/Output (I/O) conductors, wherein the I/O conductors pass through a hermetic seal such that a first end of the I/O conductors resides on a non-hermetic side of the hermetic seal and a second end of the I/O conductors resides on a hermetic side of the hermetic seal within a hermetically sealed interior of a hermetically sealed metal case of the apparatus; a printed circuit interconnect substrate residing on the hermetic side of the hermetic seal, wherein the printed circuit interconnect substrate includes a multi-layer circuit board comprising a buried signal layer between first and second conductive layers, wherein each conductive layer is electrically connected to a constant voltage to form a constant voltage plane, wherein the multi-layer circuit board is arranged substantially parallel to the hermetic seal and normal to the I/O conductors to provide electrical shielding, and wherein one I/O conductor provides an electrical connection to the constant voltage plane; and one or more ceramic chip capacitors mounted on the printed circuit interconnect substrate and mounted within the hermetically sealed interior of the hermetically sealed metal case, wherein a first end of each capacitor is electrically connected via printed circuit interconnect to the second end of an I/O conductor and a second end of each capacitor is electrically connected via the printed circuit interconnect to the metal case. 2. The apparatus of claim 1, wherein the printed circuit interconnect substrate is mounted on the hermetic side of the hermetic seal. 3. The apparatus of claim 1, wherein the printed circuit interconnect substrate includes a printed circuit board material. 4. The apparatus of claim 1, wherein the printed circuit interconnect substrate includes flexible circuit tape. 5. The apparatus of claim 1, wherein the printed circuit interconnect substrate is a multi-layer substrate. 6. The apparatus of claim 1, wherein the printed circuit interconnect substrate includes an electrically conductive medium. 7. The apparatus of claim 1, wherein the capacitors have a dielectric breakdown voltage of about 1200 volts. 8. The apparatus of claim 1, wherein the capacitors have a dielectric breakdown voltage within a range of about 200 to 1500 volts. 9. The apparatus of claim 1, wherein the capacitors are discrete capacitors. 10. The apparatus of claim 1, wherein the capacitors are included in a multi-chip package. 11. The apparatus of claim 1, wherein the capacitors are adapted to filter electromagnetic interference. 12. The apparatus of claim 1, wherein the hermetic seal is part of an implantable medical device. 13. The apparatus of claim 1, wherein the I/O conductors are pins. 14. The apparatus of claim 1 wherein the I/O conductors are wires. 15. The apparatus of claim 1 wherein the I/O conductors are conductive traces. 16. The apparatus of claim 3, wherein the printed circuit board material includes a ceramic. 17. The apparatus of claim 3, wherein the printed circuit board material includes FR4. 18. The apparatus of claim 4, wherein the flexible circuit tape includes polyimide. 19. The apparatus of claim 6, wherein the electrically conductive medium includes solder. 20. The apparatus of claim 6, wherein the electrically conductive medium includes conductive epoxy. 21. The apparatus of claim 6, wherein the electrically conductive medium includes wire-bonds. 22. The apparatus of claim 9, wherein the capacitors include surface mount packaging. 23. The apparatus of claim 12, wherein the hermetic seal includes a ceramic. 24. The apparatus of claim 12, wherein the hermetic seal includes an epoxy. 25. The apparatus of claim 12, wherein the hermetic seal includes a glass. 26. The apparatus of claim 15, wherein the conductive traces are included in a printed circuit interconnect that accommodates surface mounting of electronic components.
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이 특허에 인용된 특허 (41)
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