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Systems, methods, and computer program products for providing a two-bit symbol bus error correcting code 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H03M-013/29
출원번호 UP-0421534 (2006-06-01)
등록번호 US-7721178 (2010-06-10)
발명자 / 주소
  • Dell, Timothy J.
  • Meaney, Patrick J.
출원인 / 주소
  • International Business Machines Corporation
대리인 / 주소
    Cantor Colburn LLP
인용정보 피인용 횟수 : 5  인용 특허 : 54

초록

Systems, methods and computer program products for providing a nested two-bit symbol bus error correcting code. Methods include constructing a nested error correcting code (ECC) scheme. The method includes receiving a Hamming distance n code. A symbol correcting code H-matrix is created by iterative

대표청구항

The invention claimed is: 1. A computer implemented method of constructing a nested error correcting code (ECC) scheme, the method comprising: receiving in a computer system a Hamming distance n code; and creating in the computer system a symbol correcting code H-matrix by iteratively adding rows o

이 특허에 인용된 특허 (54)

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  9. Honda, Toshiyuki, ECC circuit-containing semiconductor memory device and method of testing the same.
  10. Holman Thomas J., Encoder and decoder for an SEC-DED-S4ED rotational code.
  11. Olarig Sompong P., Error checking and correcting for burst DRAM devices.
  12. Chen Chin-Long (Wappingers Falls NY), Error correcting code for 8-bit-per-chip memory with reduced redundancy.
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  32. Dell Timothy J. ; Faucher Marc R. ; Hazelzet Bruce G., Method and apparatus for ECC bus protection in a computer system with non-parity memory.
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  37. Zook Christopher P., Method and apparatus for flash burst error correction.
  38. Olarig Sompong P., Method and apparatus for performing error detection and correction with memory devices.
  39. Cheng Joe-Ming ; Singh Shanker, Method and apparatus for performing on-chip function checks and locating detected anomalies within a nested time interval using CRCs or the like.
  40. Berry, Robert Francis; Levine, Frank Eliot; Urguhart, Robert J., Method and system for periodic trace sampling for real-time generation of segments of call stack trees augmented with call stack position determination.
  41. Reiff Francis H. (Manitou Springs CO), Method for addressing a block addressable memory using a gray code.
  42. Hall Christopher ; Sewal Rajat ; Muwafi Jumana, Modular re-useable bus architecture.
  43. Hammons, Jr.,A. Roger, Multi-dimensional irregular array codes and methods for forward error correction, and apparatuses and systems employing such codes and methods.
  44. Weng Lih-Jyh (Lexington MA), Multi-level error correction system.
  45. Riggle Charles M. (Acton MA) Weng Lih-Jyh (Lexington MA) Field Norman A. (Maynard MA), Multiple error detecting and correcting system employing Reed-Solomon codes.
  46. Uehara Izushi (Tokyo JPX), Multiprocessor system with a fault locator.
  47. Peterson Bruce R. (San Jose CA) Nguyen Hung C. (San Jose CA) Machado Michael G. (San Jose CA), On-the-fly error correction with embedded digital controller.
  48. Mo Shih ; Chang Stanley, Pipelined error correction for minimizing disk re-reading in hard drives.
  49. Chin-Long Chen ; Mu-Yue Hsiao ; Patrick J. Meaney ; William Wu Shen, Single symbol correction double symbol detection code employing a modular H-matrix.
  50. DeLong Rance J., Structured exception-handling methods, apparatus, and computer program products.
  51. Karim Faraydon O. (Vestal NY), System for multiple error detection with single and double bit error correction.
  52. Dell,Timothy J.; Gower,Kevin C.; Maule,Warren E., System, method and storage medium for providing fault detection and correction in a memory subsystem.
  53. Yedidia,Jonathan S.; Chen,Jinghu, Transforming generalized parity check matrices for error-correcting codes.
  54. Chen Chin L. (Wappingers Falls NY), Two bit symbol SEC/DED code.

이 특허를 인용한 특허 (5)

  1. Ish-Shalom, Tomer; Teitel, Moti, Efficient coding with single-error correction and double-error detection capabilities.
  2. Ambroladze, Ekaterina M.; Meaney, Patrick J.; O'Neill, Jr., Arthur J., High performance cache directory error correction code.
  3. Nakao, Yoshihiro; Kimura, Isao, Information processing device and information processing method.
  4. Chung, Hoe-Ju; Kim, Kyu-Hyoun, Method of detecting error in a semiconductor memory device.
  5. Chung, Hoe-Ju; Kim, Kyu-Hyoun, Semiconductor memory device and memory system including the same.
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