초록 ▼

Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C3MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, XOR gates, latches, flip-flops and the like ar

Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C3MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, XOR gates, latches, flip-flops and the like are implemented using C3MOS techniques. Optimum balance between power consumption and speed for each circuit application is achieve by combining high speed C3MOS logic with low power conventional CMOS logic. The combined C3MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems.

대표청구항 ▼

What is claimed is: 1. A multi-channel serial link circuit, comprising: a first deserializer circuit block, implemented using current-controlled complementary metal-oxide semiconductor (C3MOS) logic, that is operable to convert a first differential input signal into a first deserialized signal that

What is claimed is: 1. A multi-channel serial link circuit, comprising: a first deserializer circuit block, implemented using current-controlled complementary metal-oxide semiconductor (C3MOS) logic, that is operable to convert a first differential input signal into a first deserialized signal that includes a first plurality of signals; and a second deserializer circuit block, implemented in a parallel configuration with respect to the first deserializer circuit block and implemented using C3MOS logic, that is operable to convert a second differential input signal into a second deserialized signal that includes a second plurality of signals. 2. The multi-channel serial link circuit of claim 1, wherein: within each of the first deserializer circuit block and the second deserializer circuit block, logic levels are signaled by current steering in one of two or more branches in response to a differential input signal. 3. The multi-channel serial link circuit of claim 1, wherein: the first differential input signal that has a first frequency; and each of the first plurality of signals has a second frequency. 4. The multi-channel serial link circuit of claim 3, wherein: the second frequency is less than the first frequency. 5. The multi-channel serial link circuit of claim 3, wherein: the first frequency is an integer multiple of the second frequency. 6. The multi-channel serial link circuit of claim 1, wherein: the first differential input signal has a first frequency; the second differential input signal has the first frequency; each of the first plurality of signals has a second frequency; and each of the second plurality of signals has the second frequency. 7. The multi-channel serial link circuit of claim 1, further comprising: a processing circuit block, coupled to the first deserializer circuit block and the second deserializer circuit block and implemented using conventional complementary metal-oxide-semiconductor (CMOS) logic wherein substantially zero static current is dissipated, that is operable to generate a plurality of processed signals. 8. The multi-channel serial link circuit of claim 7, wherein: the first deserializer circuit block, the second deserializer circuit block, and the processing circuit block are all implemented on a single silicon die. 9. The multi-channel serial link circuit of claim 7, wherein: the first differential input signal has a first frequency; the second differential input signal has the first frequency; each of the first plurality of signals has a second frequency; each of the second plurality of signals has the second frequency; and each of the plurality of processed signals has the second frequency. 10. The multi-channel serial link circuit of claim 9, wherein: the second frequency is less than the first frequency. 11. The multi-channel serial link circuit of claim 9, wherein: the first frequency is an integer multiple of the second frequency. 12. The multi-channel serial link circuit of claim 7, further comprising: a first serializer circuit block, coupled to the processing circuit block and implemented using C3MOS logic, that is operable to convert a first portion of the plurality of processed signals into a first serialized signal; and a second serializer circuit block, coupled to the processing circuit block, implemented in a parallel configuration with respect to the first serializer circuit block, and implemented using C3MOS logic, that is operable to convert a second portion of the plurality of processed signals into a second serialized signal. 13. The multi-channel serial link circuit of claim 12, wherein: the first differential input signal has a first frequency; the second differential input signal has the first frequency; each of the first plurality of signals has a second frequency; each of the second plurality of signals has the second frequency; each of the plurality of processed signals has the second frequency; the first serialized signal has a third frequency; and the second serialized signal has the third frequency. 14. The multi-channel serial link circuit of claim 13, wherein: the first frequency is the third frequency. 15. The multi-channel serial link circuit of claim 13, wherein: the second frequency is less than the first frequency. 16. The multi-channel serial link circuit of claim 13, wherein: the first frequency is an integer multiple of the second frequency. 17. The multi-channel serial link circuit of claim 1, wherein: the multi-channel serial link circuit is implemented within a fiber optic channel. 18. The multi-channel serial link circuit of claim 1, wherein: the first deserializer circuit block and the second deserializer circuit block are both implemented on a single silicon die. 19. A multi-channel serial link circuit, comprising: a first serializer circuit block, implemented using current-controlled complementary metal-oxide semiconductor (C3MOS) logic, that is operable to convert a first portion of a plurality of signals into a first serialized signal; and a second serializer circuit block, implemented in a parallel configuration with respect to the first serializer circuit block and implemented using C3MOS logic, that is operable to convert a second portion of the plurality of signals into a second serialized signal. 20. The multi-channel serial link circuit of claim 19, wherein: within each of the first serializer circuit block and the second serializer circuit block, logic levels are signaled by current steering in one of two or more branches in response to a differential input signal. 21. The multi-channel serial link circuit of claim 19, wherein: each of the plurality of signals has a first frequency; and the first serialized signal has a second frequency. 22. The multi-channel serial link circuit of claim 21, wherein: the second frequency is greater than the first frequency. 23. The multi-channel serial link circuit of claim 21, wherein: the second frequency is an integer multiple of the first frequency. 24. The multi-channel serial link circuit of claim 19, further comprising: a processing circuit block, coupled to each of the first serializer circuit block and the second serializer circuit block and implemented using conventional complementary metal-oxide-semiconductor (CMOS) logic wherein substantially zero static current is dissipated, that is operable to generate the plurality of signals. 25. The multi-channel serial link circuit of claim 24, wherein: the first serializer circuit block, the second serializer circuit block, and the processing circuit block are all implemented on a single silicon die. 26. The multi-channel serial link circuit of claim 24, wherein: each of the plurality of signals has a first frequency; the first serialized signal has a second frequency; the second serialized signal has the second frequency. 27. The multi-channel serial link circuit of claim 26, wherein: the second frequency is greater than the first frequency. 28. The multi-channel serial link circuit of claim 26, wherein: the second frequency is an integer multiple of the first frequency. 29. The multi-channel serial link circuit of claim 19, wherein: the multi-channel serial link circuit is implemented within a fiber optic channel. 30. The multi-channel serial link circuit of claim 19, wherein: the first serializer circuit block and the second serializer circuit block are both implemented on a single silicon die. 31. A multi-channel serial link circuit, comprising: a first deserializer circuit block, implemented using current-controlled complementary metal-oxide semiconductor (C3MOS) logic, that is operable to convert a first differential input signal into a first deserialized signal that includes a first plurality of signals; and a second deserializer circuit block, implemented in a parallel configuration with respect to the first deserializer circuit block and implemented using C3MOS logic, that is operable to convert a second differential input signal into a second deserialized signal that includes a second plurality of signals; and a processing circuit block, coupled to each of the first deserializer circuit block and the second deserializer circuit block and implemented using conventional complementary metal-oxide-semiconductor (CMOS) logic wherein substantially zero static current is dissipated, that is operable to generate a plurality of processed signals; a first serializer circuit block, coupled to the processing circuit block and implemented using C3MOS logic, that is operable to convert a first portion of the plurality of processed signals into a first serialized signal; and a second serializer circuit block, coupled to the processing circuit block, implemented in a parallel configuration with respect to the first serializer circuit block, and implemented using C3MOS logic, that is operable to convert a second portion of the plurality of processed signals into a second serialized signal; and wherein: the first differential input signal has a first frequency; the second differential input signal has the first frequency; each of the first plurality of signals has a second frequency; each of the second plurality of signals has the second frequency; each of the plurality of processed signals has the second frequency; and the first serialized signal has a third frequency; and the second serialized signal has the third frequency. 32. The multi-channel serial link circuit of claim 31, wherein: the first frequency is the third frequency. 33. The multi-channel serial link circuit of claim 31, wherein: the second frequency is less than the first frequency. 34. The multi-channel serial link circuit of claim 31, wherein: the first frequency is an integer multiple of the second frequency. 35. The multi-channel serial link circuit of claim 31, wherein: the multi-channel serial link circuit is implemented within a fiber optic channel. 36. The multi-channel serial link circuit of claim 31, wherein: the first deserializer circuit block, the second deserializer circuit block, the processing circuit block, the first serializer circuit block, and the second serializer circuit block are all implemented on a single silicon die. 37. An apparatus, comprising: a first stage for deserializing a differential serialized signal thereby generating a first deserialized signal that includes a first plurality of signals, wherein the first stage includes a current-controlled complementary metal-oxide semiconductor (C3MOS) circuit having a first metal-oxide semiconductor (MOS) transistor with a first drain, a first gate, and a first source and a second MOS transistor with a second drain, a second gate, and a second source, wherein: a current steering circuit within the C3MOS circuit includes the first source and the second source; the first source and the second source are coupled together and to a current source; and the first drain and the second drain are coupled to a power supply; and a second stage, coupled to the first stage, for processing the first deserialized signal thereby generating a second deserialized signal that includes a second plurality of signals. 38. The apparatus of claim 37, wherein: the first source and second source are coupled to at least one additional power supply via the current source. 39. The apparatus of claim 37, wherein: the current source is coupled to at least one additional power supply. 40. The apparatus of claim 37, wherein: current steering is performed within the current steering circuit in response to the differential serialized signal being provided to the first gate and the second gate. 41. The apparatus of claim 37, wherein: the first drain is coupled to the power supply via a first resistive load; and the second drain is coupled to the power supply via a second resistive load. 42. The apparatus of claim 37, wherein: the second stage is implemented using conventional complementary metal-oxide-semiconductor (CMOS) logic. 43. The apparatus of claim 37, further comprising: a third stage, coupled to the second stage, for serializing the second deserialized signal thereby generating a serialized signal. 44. The apparatus of claim 43, wherein: the third stage includes at least one additional C3MOS circuit having a third MOS transistor with a third drain, a third gate, and a third source and a fourth MOS transistor with a fourth drain, a fourth gate, and a fourth source, wherein: current steering is performed among one or more branches of the at least one additional C3MOS circuit in response to at least one additional differential serialized signal being provided to the third gate and the fourth gate; the third source and the fourth source are coupled together and to at least one additional current source; and the third drain and the fourth drain are coupled to the power supply. 45. The apparatus of claim 44, wherein: the third drain is coupled to the power supply via a first resistive load; and the fourth drain is coupled to the power supply via a second resistive load. 46. The apparatus of claim 44, wherein: the third MOS transistor and the fourth MOS transistor are n-channel MOS transistors. 47. The apparatus of claim 43, wherein: the differential serialized signal has a first frequency; each of the first plurality of signals has a second frequency; each of the second plurality of signals has the second frequency; and the serialized signal has a third frequency. 48. The apparatus of claim 47, wherein: the first frequency is the third frequency. 49. The apparatus of claim 47, wherein: the first frequency is an integer multiple of the second frequency. 50. The apparatus of claim 47, wherein: the third frequency is an integer multiple of the second frequency. 51. The apparatus of claim 37, wherein: the differential serialized signal has a first frequency; each of the first plurality of signals has a second frequency; and each of the second plurality of signals has the second frequency. 52. The apparatus of claim 51, wherein: the first frequency is an integer multiple of the second frequency. 53. The apparatus of claim 37, wherein: the first MOS transistor and the second MOS transistor are n-channel MOS transistors. 54. The apparatus of claim 37, wherein: the current source includes an n-channel MOS transistor having a third gate for receiving a signal that corresponds to a clock signal. 55. The apparatus of claim 37, wherein: the current source includes an n-channel MOS having a third drain; and the first source and the second source are connected together and to the third drain. 56. The apparatus of claim 37, wherein: the first stage and the second stage are implemented on a single silicon die. 57. The apparatus of claim 37, wherein: the apparatus is implemented within a fiber optic channel. 58. The apparatus of claim 37, wherein: the first deserialized signal that includes the first plurality of signals is a first parallel n-bit signal such that each of the first plurality of signals corresponds to one respective bit of the first parallel n-bit signal; the second deserialized signal that includes the second plurality of signals is a second parallel n-bit signal such that each of the second plurality of signals corresponds to one respective bit of the second parallel n-bit signal; and n is an integer. 59. An apparatus, comprising: a first stage for processing a first deserialized signal that includes a first plurality of signals thereby generating a second deserialized signal that includes a second plurality of signals; a second stage, coupled to the first stage, for serializing the second deserialized signal thereby generating a serialized signal, wherein the second stage includes a current-controlled complementary metal-oxide semiconductor (C3MOS) circuit having a first metal-oxide semiconductor (MOS) transistor with a first drain, a first gate, and a first source and a second MOS transistor with a second drain, a second gate, and a second source, wherein: a current steering circuit within the C3MOS circuit includes the first source and the second source; the first source and the second source are coupled together and to a current source; and the first drain and the second drain are coupled to a power supply. 60. The apparatus of claim 59, wherein: the first source and second source are coupled to at least one additional power supply via the current source. 61. The apparatus of claim 59, wherein: the current source is coupled to at least one additional power supply. 62. The apparatus of claim 59, wherein: current steering is performed within the current steering circuit in response to a differential serialized signal being provided to the first gate and the second gate. 63. The apparatus of claim 59, wherein: the first drain is coupled to the power supply via a first resistive load; and the second drain is coupled to the power supply via a second resistive load. 64. The apparatus of claim 59, wherein: the first stage is implemented using conventional complementary metal-oxide-semiconductor (CMOS) logic. 65. The apparatus of claim 59, further comprising: a third stage, coupled to the first stage, for processing at least one additional serialized signal thereby generating the first deserialized signal that includes the first plurality of signals. 66. The apparatus of claim 65, wherein: the third stage includes at least one additional C3MOS circuit having a third MOS transistor with a third drain, a third gate, and a third source and a fourth MOS transistor with a fourth drain, a fourth gate, and a fourth source, wherein: current steering is performed among one or more branches of the at least one additional C3MOS circuit in response to at least one additional differential signal being provided to the third gate and the fourth gate; the third source and the fourth source are coupled together and to at least one additional current source; and the third drain and the fourth drain are coupled to the power supply. 67. The apparatus of claim 66, wherein: the third drain is coupled to the power supply via a first resistive load; and the fourth drain is coupled to the power supply via a second resistive load. 68. The apparatus of claim 66, wherein: the third MOS transistor and the fourth MOS transistor are n-channel MOS transistors. 69. The apparatus of claim 65, wherein: the at least one additional serialized signal has a first frequency; each of the first plurality of signals has a second frequency; each of the second plurality of signals has the second frequency; and the serialized signal has a third frequency. 70. The apparatus of claim 69, wherein: the first frequency is the third frequency. 71. The apparatus of claim 69, wherein: the first frequency is an integer multiple of the second frequency. 72. The apparatus of claim 69, wherein: the third frequency is an integer multiple of the second frequency. 73. The apparatus of claim 59, wherein: each of the first plurality of signals has a first frequency; each of the second plurality of signals has the first frequency; and the serialized signal has a second frequency. 74. The apparatus of claim 73, wherein: the second frequency is an integer multiple of the first frequency. 75. The apparatus of claim 59, wherein: the first MOS transistor and the second MOS transistor are n-channel MOS transistors. 76. The apparatus of claim 59, wherein: the current source includes an n-channel MOS having a third gate for receiving a signal that corresponds to a clock signal. 77. The apparatus of claim 59, wherein: the current source includes an n-channel MOS having a third drain; and the first source and the second source are connected together and to the third drain. 78. The apparatus of claim 59, wherein: the first stage and the second stage are implemented on a single silicon die. 79. The apparatus of claim 59, wherein: the apparatus is implemented within a fiber optic channel. 80. The apparatus of claim 59, wherein: the first deserialized signal that includes the first plurality of signals is a first parallel n-bit signal such that each of the first plurality of signals corresponds to one respective bit of the first parallel n-bit signal; the second deserialized signal that includes the second plurality of signals is a second parallel n-bit signal such that each of the second plurality of signals corresponds to one respective bit of the second parallel n-bit signal; and n is an integer. 81. An apparatus, comprising: a first circuit, that includes n latches, for deserializing a differential signal received at a first frequency thereby generating a parallel n-bit signal, wherein: n is an integer; each of the n latches is implemented for receiving the differential signal and a clock signal; the n latches are implemented for outputting the parallel n-bit signal at a second frequency; and each of the n latches includes a respective current steering circuit that includes a respective current source having an input for receiving the clock signal; and a second circuit, coupled to the first circuit, for processing the parallel n-bit signal; and wherein: the second circuit is implemented using conventional complementary metal-oxide-semiconductor (CMOS) logic; and the first frequency is n times the second frequency. 82. The apparatus of claim 81, wherein: each of the n latches respectively includes a first metal-oxide semiconductor (MOS) transistor with a first drain, a first gate, and a first source and a second MOS transistor with a second drain, a second gate, and a second source, wherein within each of the n latches: the differential signal is provided to the first gate and the second gate; the first source and the second source are coupled together and to the respective current source; and the first drain and the second drain are coupled to a power supply. 83. The apparatus of claim 82, wherein: the first MOS transistor and the second MOS transistor are n-channel MOS transistors. 84. The apparatus of claim 82, wherein: the first drain is coupled to the power supply via a first resistive load; and the second drain is coupled to the power supply via a second resistive load. 85. The apparatus of claim 81, further comprising: a third circuit, coupled to the second circuit, for serializing the processed parallel n-bit signal output from the second circuit. 86. The apparatus of claim 85, wherein: the third circuit includes at least one additional current source, a first metal-oxide semiconductor (MOS) transistor with a first drain, a first gate, and a first source and a second MOS transistor with a second drain, a second gate, and a second source, wherein within each of the n latches: at least one additional differential signal is provided to the first gate and the second gate; the first source and the second source are coupled together and to the at least one additional current source; and the first drain and the second drain are coupled to a power supply. 87. The apparatus of claim 86, wherein: the third drain is coupled to the power supply via a first resistive load; and the fourth drain is coupled to the power supply via a second resistive load. 88. The apparatus of claim 86, wherein: the first MOS transistor and the second MOS transistor are n-channel MOS transistors. 89. The apparatus of claim 81, further comprising: a third circuit for deserializing at least one additional differential signal received at a third frequency thereby generating at least one additional parallel n-bit signal. 90. The apparatus of claim 89, wherein: the first frequency is the third frequency. 91. The apparatus of claim 81, further comprising: at least one additional circuit that includes at least one additional current steering circuit. 92. The apparatus of claim 81, wherein: the first circuit and the second circuit are implemented on a single silicon die. 93. The apparatus of claim 81, wherein: the apparatus is implemented within a fiber optic channel.