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특허 상세정보

MyON담기
내보내기 페이스북 공유 카카오톡 공유

Distributed and recoverable digital control system

특허상세정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판) G06F-011/00    G06F-007/00    B64C-019/00   
미국특허분류(USC) 701/001; 701/003; 701/029; 701/031; 701/036; 244/075.1; 244/194; 714/002; 714/011
출원번호 UP-0381608 (2006-05-04)
등록번호 US-7725215 (2010-06-14)
발명자 / 주소
출원인 / 주소
대리인 / 주소
    Fogg & Powers LLC
인용정보 피인용 횟수 : 7  인용 특허 : 41
초록
▼

A real-time multi-tasking digital control system with rapid recovery capability is disclosed. The control system includes a plurality of computing units comprising a plurality of redundant processing units, with each of the processing units configured to generate one or more redundant control commands. One or more internal monitors are employed for detecting data errors in the control commands. One or more recovery triggers are provided for initiating rapid recovery of a processing unit if data errors are detected. The control system also includes a plur...

대표
청구항
▼

What is claimed is: 1. A digital control system, comprising: an integrated modular computing platform comprising: a plurality of computing units comprising: a plurality of redundant processing units, each of the processing units configured to generate one or more redundant control commands and execute a plurality of different applications that are time and space partitioned; one or more internal monitors for detecting one or more data errors in the control commands and in application state data; and one or more recovery triggers for initiating rapid rec...

이 특허에 인용된 특허 (41)

  1. Davies,Ian Robert. Apparatus and method for a server deterministically killing a redundant server integrated within the same network storage appliance chassis. USP2008077401254.
  2. Long,Finbarr Denis; Ardini,Joseph; Kirkpatrick,Dana A.; O'Keeffe,Michael James. Apparatus and methods for fault-tolerant computing using a switching fabric. USP2006067065672.
  3. Reid Robert (Dunstable MA). Central processing apparatus for fault-tolerant computing. USP1984064453215.
  4. Slegel Timothy John ; Murray Robert E.. Computer system with transparent processor sparing. USP2000096115829.
  5. Larry J. Yount. Critical control adaption of integrated modular architecture. USP2002046367031.
  6. LeCren,Andrew Thomas. Dynamic reallocation of processing resources for redundant functionality. USP2006016990320.
  7. Lorch,Jacob R.; Howell,Jonathan R.; Douceur,John R.. Efficient changing of replica sets in distributed fault-tolerant computing system. USP2008027334154.
  8. Sampson Neil L. ; Gray Scott L. ; Walker Gary. Error detection and correction for data stored across multiple byte-wide memory devices. USP1999065909541.
  9. Marshall Joseph R. ; Langston Dale G.. Error detection and fault isolation for lockstep processor systems. USP2000056065135.
  10. Marshall Joseph R. ; Langston Dale G.. Error detection and fault isolation for lockstep processor systems. USP1999065915082.
  11. James Stevens Klecka ; William F. Bruckert ; Robert L. Jardine. Error self-checking and recovery using lock-step processor pair architecture. USP2002056393582.
  12. Hay Rick H. (Cave Creek AZ) Smith Clarence S. (Glendale AZ) Girts Robert D. (Mesa AZ) Yount Larry J. (Scottsdale AZ). Fail-operational fault tolerant flight critical computer architecture and monitoring method. USP1996085550736.
  13. Andress, Sidney L.; Andes, Curtis D.; Rightnour, Gerald E.; Smith, James R.. Fast relief swapping of processors in a data processing system. USP2003066574748.
  14. Hess Richard F. (Glendale AZ) Yount Larry J. (Scottsdale AZ). Fault recoverable computer system. USP1994055313625.
  15. Hess Richard F. (Glendale AZ) Liebel Kurt A. (Phoenix AZ) Yount Larry J. (Phoenix AZ). Fault recovery mechanism, transparent to digital system function. USP1991024996687.
  16. Bissett Thomas D. ; Leveille Paul A. ; Muench Erik. Fault resilient/fault tolerant computing. USP2001086279119.
  17. Fuchs Stephen ; Wardrop Andrew J.. Fault tolerant computer system. USP2000106141770.
  18. Wardrop Andrew J.. Fault tolerant computer system. USP1999055903717.
  19. Frank M. G. Doerenberg ; Michael Topic. Fault tolerant data communication network. USP2002106467003.
  20. Gray Scott L. (Glendale AZ) Thompson Steven R. (Phoenix AZ). Fault-tolerant digital computing system with reduced memory redundancy. USP1992025086429.
  21. Quach, Nhon. Firmware mechanism for correcting soft errors. USP2003096625749.
  22. Hess, Richard. High integrity control system architecture using digital computing platforms with rapid recovery. USP2004116813527.
  23. Hess Richard F. (Scottsdale AZ). High integrity digital processor architecture. USP1988064751670.
  24. Loise, Dominique; Ledoux, Jean-Pierre; Sardier, Patrick. Low cost modular architecture for piloting an aerodyne operating with high level of security. USP2003076600963.
  25. Hess Richard F. ; Smith Clarence Scott. Memory with high integrity memory cells. USP2000126163480.
  26. Hofstee, Harm Peter; Nair, Ravi. Method and apparatus for computer system reliability. USP2004066751749.
  27. Murphy Declan J. ; Talluri Madhusudhan ; Matena Vladimir ; Khalidi Yousef A. ; Bernabeu-Auban Jose M.,ESX ; Tucker Andrew G.. Method and apparatus for transparent server failover for highly available objects. USP2001026185695.
  28. Bossen Douglas Craig ; Chandra Arun. Method and system for fault-handling to improve reliability of a data-processing system. USP2000056058491.
  29. Shinohara,Tomohiro; Furuya,Hodaka; Sunada,Yoji. Method and system for installing program in multiple system. USP2006067062676.
  30. Chrabaszcz Michael. Method for clustering software applications. USP2000106134673.
  31. Spaur Charles W. ; Braitberg Michael F. ; Kennedy Patrick J. ; Hatcher Lester B.. Mobile portable wireless communication system. USP1998035732074.
  32. Dhong, Sang Hoo; Hofstee, Harm Peter; Nair, Ravi; Posluszny, Steven Douglas. Multiprocessor with pair-wise high reliability mode, and method therefore. USP2004086772368.
  33. Winger, John M.; Green, David; Ohran, Richard S.; Ohran, Michael R.. Operation of a standby server to preserve data stored by a network server. USP2003056560617.
  34. De Bonis-Hamelin, Marie-Antoinette; Menyhart, Zoltan; Sorace, Jean-Dominique. Process for reconfiguring an information processing system upon detection of a component failure. USP2004096789214.
  35. Greenwood Thomas A. ; Pastusak Thomas W.. Real-time orientation of machine media to improve machine accuracy. USP1999095949685.
  36. Thuy Pham D. (Chatenay Malabry FRX). Self-monitored process control device. USP1982084345327.
  37. Pittelkow,Michael Henry; Olson,Mark David. System and method for a reserved memory area shared by all redundant storage controllers. USP2006027003688.
  38. Gawali,Ashish L.. System and method to automate replication in a clustered environment. USP2008017320088.
  39. Fung,Priscilla C.; Somogyi,Alexander J.. System for highly available transaction recovery for transaction processing systems. USP2007027178050.
  40. Slegel Timothy John ; Murray Robert E.. Transparent processor sparing. USP2001026189112.
  41. Minto Karl Dean. Triplex control system with sensor failure compensation. USP1998055757641.

이 특허를 인용한 특허 피인용횟수: 7

  1. Le Bastard, Jean-Claude. Device for compensating for the mechanical play of a helicopter flight control. USP2010127857262.
  2. Corcoran, James J.; Danielson, Eric J.; Hemaidan, Samir S.; Roltgen, John W.; Sisson, James E.; Kovalan, Mark A.; Singer, Mark C.. Dissimilar processor synchronization in fly-by-wire high integrity computing platforms and displays. USP2011098015390.
  3. Sghairi, Manel; Brot, Patrice; Aubert, Jean-Jacques; De Bonneval, Agnan; Crouzet, Yves. Flight control system and aircraft comprising it. USP2014068761969.
  4. Strietzel, Roland; Michel, Klaus; Ratzsch, Dietmar. Method for increasing the reliability of sensor systems. USP2017039593951.
  5. Stange, Kent. Methods and systems for translating an emergency system alert signal to an automated flight system maneuver. USP2018019870000.
  6. Manfred, Mark T.; Ryno, Thomas A.. Systems and methods of redundancy for aircraft inertial signal data. USP2012068204635.
  7. Davies, Steven P.. Vehicle including a processor system having fault tolerance. USP2011027890797.

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