IPC분류정보
국가/구분 |
United States(US) Patent
등록
|
국제특허분류(IPC7판) |
|
출원번호 |
UP-0039161
(2005-01-20)
|
등록번호 |
US-7732923
(2010-06-29)
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발명자
/ 주소 |
- Wu, Zhen-Cheng
- Lu, Yung-Cheng
- Ko, Chung-Chi
|
출원인 / 주소 |
- Taiwan Semiconductor Manufacturing Company, Ltd.
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대리인 / 주소 |
|
인용정보 |
피인용 횟수 :
1 인용 특허 :
9 |
초록
▼
An ultra-violet (UV) protection layer is formed over a semiconductor workpiece before depositing a UV curable dielectric layer. The UV protection layer prevents UV light from reaching and damaging underlying material layers and electrical devices. The UV protection layer comprises a layer of silicon
An ultra-violet (UV) protection layer is formed over a semiconductor workpiece before depositing a UV curable dielectric layer. The UV protection layer prevents UV light from reaching and damaging underlying material layers and electrical devices. The UV protection layer comprises a layer of silicon doped with an impurity, wherein the impurity comprises O, C, H, N, or combinations thereof. The UV protection layer may comprise SiOC:H, SiON, SiN, SiCO:H, combinations thereof, or multiple layers thereof, as examples.
대표청구항
▼
What is claimed is: 1. A semiconductor device, comprising: a workpiece; a gate disposed over the workpiece; a first ultra-violet (UV) protection layer over the gate, wherein a non-planar portion of the first UV protection layer abuts and conforms to the gate, and wherein the first UV protection lay
What is claimed is: 1. A semiconductor device, comprising: a workpiece; a gate disposed over the workpiece; a first ultra-violet (UV) protection layer over the gate, wherein a non-planar portion of the first UV protection layer abuts and conforms to the gate, and wherein the first UV protection layer comprises at least one layer of silicon doped with oxygen (O), carbon (C), hydrogen (H), nitrogen (N), or combinations thereof; a second UV protection layer over the first UV protection layer, wherein a portion of the second UV protection layer conforms to the non-planar portion of the first UV protection layer; and a contact etch stop layer over the second UV protection layer. 2. The semiconductor device according to claim 1, further comprising an electrical device formed within or over the workpiece. 3. The semiconductor device according to claim 2, wherein the electrical device comprises a transistor or a capacitor. 4. The semiconductor device according to claim 1, further comprising a source or drain of a transistor formed in the workpiece, wherein the first UV protection layer is disposed over and abuts the source or drain of the transistor. 5. The semiconductor device according to claim 1 further comprising a dielectric layer over the contact etch stop layer. 6. The semiconductor device according to claim 5, wherein the dielectric layer comprises a dielectric material having a dielectric constant of about 3.0 or less. 7. The semiconductor device according to claim 5, wherein the dielectric layer comprises undoped silicate glass (USG). 8. The semiconductor device according to claim 1, wherein the first UV protection layer comprises oxygen and carbon, and wherein an oxygen content is greater than a carbon content. 9. A semiconductor device, comprising: a workpiece; a gate disposed over the workpiece; a contact etch stop layer over and abutting the gate; and an ultra-violet (UV) protection layer over the contact etch stop layer, wherein the UV protection layer abuts and conforms to a non-planar portion of the etch stop layer, and wherein the UV protection layer comprises at least one layer of silicon doped with oxygen (O), carbon (C), hydrogen (H), nitrogen (N), or combinations thereof. 10. The semiconductor device according to claim 9, wherein the semiconductor device includes an electrical device formed within or over the workpiece. 11. The semiconductor device according to claim 9 further comprising a dielectric layer over the UV protection layer. 12. The semiconductor device according to claim 11, wherein the dielectric layer comprises a pre-metal dielectric (PMD) disposed over the UV protection layer. 13. The semiconductor device according to claim 9, wherein the semiconductor device comprises a pre-metal dielectric (PMD) disposed over the workpiece, and wherein the UV protection layer is disposed within the pre-metal dielectric. 14. The semiconductor device according to claim 9, further comprising a pre-metal dielectric (PMD) disposed over the workpiece, and wherein the UV protection layer is disposed over the pre-metal dielectric. 15. The semiconductor device according to claim 14, further comprising an etch stop layer disposed over the UV protection layer. 16. The semiconductor device according to claim 9, wherein the semiconductor device comprises an inter-metal dielectric (IMD) disposed over the workpiece, and wherein the UV protection layer is disposed within the inter-metal dielectric. 17. The semiconductor device according to claim 9, further comprising an etch stop layer disposed over the workpiece, wherein the UV protection layer is disposed over the etch stop layer. 18. The semiconductor device according to claim 17, further comprising an inter-metal dielectric (IMD) disposed over the UV protection layer. 19. The semiconductor device according to claim 9, wherein the UV protection layer comprises a thickness of about 50 to 500 Å. 20. The semiconductor device according to claim 9, wherein the UV protection layer comprises a reflective index (n) of about 1.5 to 2.4. 21. The semiconductor device according to claim 9, wherein the UV protection layer comprises an absorption coefficient (k) of about 0 to 1.2. 22. The semiconductor device according to claim 9, wherein the UV protection layer comprises a layer comprising two or more layers of material. 23. The semiconductor device according to claim 9, wherein the UV protection layer comprises SiOC:H. 24. The semiconductor device according to claim 23, wherein the UV protection layer comprises a reflective index (n) of about 1.8 to 2.3 and an absorption coefficient (k) of about 0 to 1 at about 248 nm. 25. The semiconductor device according to claim 23, wherein the UV protection layer comprises a reflective index (n) of about 1.6 to 2.0 and an absorption coefficient (k) of about 0 to 1 at about 193 nm. 26. The semiconductor device according to claim 9, wherein the UV protection layer comprises SiON. 27. The semiconductor device according to claim 26, wherein the UV protection layer comprises a reflective index (n) of about 1.8 to 2.3 and an absorption coefficient (k) of about 0 to 1 at about 248 nm. 28. The semiconductor device according to claim 26, wherein the UV protection layer comprises a reflective index (n) of about 1.6 to 2.0 and an absorption coefficient (k) of about 0 to 1 at about 193 nm. 29. The semiconductor device according to claim 9, wherein the UV protection layer comprises SiN. 30. The semiconductor device according to claim 29, wherein the UV protection layer comprises a reflective index (n) of about 2.2 to 2.4 and an absorption coefficient (k) of about 0 at about 248 nm. 31. The semiconductor device according to claim 29, wherein the UV protection layer comprises a reflective index (n) of about 2.3 to 2.4 and an absorption coefficient (k) of about 0 to 1 at about 193 nm. 32. The semiconductor device according to claim 9, wherein the UV protection layer comprises SiCO:H. 33. The semiconductor device according to claim 32, wherein the UV protection layer comprises a reflective index (n) of about 2.2 to 2.4 and an absorption coefficient (k) of about 0.2 to 0.4 at about 248 nm. 34. The semiconductor device according to claim 32, wherein the UV protection layer comprises a reflective index (n) of about 1.5 to 2.3 and an absorption coefficient (k) of about 0 to 1.2 at about 193 nm. 35. The semiconductor device according to claim 9, wherein the UV protection layer comprises SiOC:H, SiON, SiN, SiCO:H, combinations thereof, or multiple layers thereof.
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