초록 ▼

An exemplary circuit for implementing conditional statements in self-timed logic circuits includes first and second logic circuits, an input circuit, an output circuit, and a pipelined routing path. The first and second logic circuits each have a self-timed input and a self-timed output. The input c

An exemplary circuit for implementing conditional statements in self-timed logic circuits includes first and second logic circuits, an input circuit, an output circuit, and a pipelined routing path. The first and second logic circuits each have a self-timed input and a self-timed output. The input circuit is coupled to provide a self-timed input signal to the self-timed input of a selected one of the first or second logic circuits based on the value of a control signal, and is further coupled to output a self-timed select signal. The output circuit is coupled to receive the self-timed output from the first logic circuit and the self-timed output from the second logic circuit, and to output a selected one of the self-timed outputs based on a value of the self-timed select signal. The pipelined routing path routes the self-timed select signal from the input circuit to the output circuit.

대표청구항 ▼

What is claimed is: 1. A circuit, comprising: a first logic circuit having a self-timed input and a self-timed output; a second logic circuit having a self-timed input and a self-timed output; an input circuit coupled to provide a self-timed input signal to the self-timed input of a selected one of

What is claimed is: 1. A circuit, comprising: a first logic circuit having a self-timed input and a self-timed output; a second logic circuit having a self-timed input and a self-timed output; an input circuit coupled to provide a self-timed input signal to the self-timed input of a selected one of the first or second logic circuits based on the value of a control signal, and further coupled to output a self-timed select signal; an output circuit coupled to receive the self-timed output from the first logic circuit and the self-timed output from the second logic circuit, and to output a selected one of the self-timed outputs based on a value of the self-timed select signal; and a pipelined routing path routing the self-timed select signal from the input circuit to the output circuit. 2. The circuit of claim 1, wherein the first logic circuit, the second logic circuit, the input circuit, and the output circuit are all implemented in programmable logic blocks substantially similar one to another. 3. The circuit of claim 2, wherein the circuit comprises an integrated circuit comprising an array of the substantially similar logic blocks. 4. The circuit of claim 3, wherein the circuit comprises a programmable logic device (PLD). 5. The circuit of claim 1, wherein a number of pipeline stages in the pipelined routing path is different from a number of pipeline stages in at least one of the first logic circuit or the second logic circuit. 6. The circuit of claim 1, wherein the number of pipeline stages in the pipelined routing path is less than the number of pipeline stages in the at least one of the first logic circuit or the second logic circuit. 7. The circuit of claim 1, wherein the input circuit implements an “IF” function between the self-timed input signal and the control signal. 8. The circuit of claim 1, wherein the output circuit implements a merge function between the self-timed outputs of the first and second logic circuits, the merge function being controlled by the self-timed select signal. 9. A circuit, comprising: a first logic circuit having a self-timed input and a self-timed output; a second logic circuit having a self-timed input and a self-timed output; an input circuit having a first self-timed output coupled to the input of the first logic circuit, a second self-timed output coupled to the input of the second logic circuit, and a self-timed select output; an output circuit having a first self-timed input coupled to the output of the first logic circuit, a second self-timed input coupled to the output of the second logic circuit, a self-timed select input, and first and second self-timed outputs; and a pipelined routing path routing a self-timed select signal from the select output of the input circuit to the select input of the output circuit, wherein the input circuit is coupled to provide a token with one of the first or second outputs based on the value of a control signal; and wherein the output circuit is coupled to provide an output token with one of the first or second outputs based on a value of the self-timed enable signal routed from the input circuit through the pipelined routing path. 10. The circuit of claim 9, wherein the first logic circuit, the second logic circuit, the input circuit, and the output circuit are all implemented in programmable logic blocks substantially similar one to another. 11. The circuit of claim 10, wherein the circuit comprises an integrated circuit comprising an array of the substantially similar logic blocks. 12. The circuit of claim 11, wherein the circuit comprises a programmable logic device (PLD). 13. The circuit of claim 1, wherein a number of pipeline stages in the pipelined routing path is different from a number of pipeline stages in at least one of the first logic circuit or the second logic circuit. 14. The circuit of claim 13, wherein the number of pipeline stages in the pipelined routing path is less than the number of pipeline stages in the at least one of the first logic circuit or the second logic circuit. 15. The circuit of claim 1, wherein the input circuit implements an “IF” function between the self-timed input signal and the control signal. 16. The circuit of claim 1, wherein the output circuit implements a merge function between the self-timed outputs of the first and second logic circuits, the merge function being controlled by the self-timed select signal. 17. An integrated circuit, comprising: an array of substantially similar programmable logic blocks; and a interconnect structure interconnecting the programmable logic blocks, wherein the array comprises: a first group of the logic blocks programmed to implement a first logic circuit having a self-timed input and a self-timed output; a second group of the logic blocks programmed to implement a second logic circuit having a self-timed input and a self-timed output; a third group of the logic blocks programmed to implement an input circuit coupled to provide the self-timed input to one of the first or second logic circuits based on the value of a control signal, and further coupled to output a self-timed select signal; and a fourth group of the logic blocks programmed to implement an output circuit coupled to receive the self-timed output from the first logic circuit and the self-timed output from the second logic circuit, and to output a selected one of the self-timed outputs based on a value of the self-timed select signal, and wherein the interconnect structure comprises a pipelined routing path routing the self-timed select signal from the input circuit to the output circuit. 18. The circuit of claim 17, wherein a number of pipeline stages in the pipelined routing path is different from a number of pipeline stages in at least one of the first logic circuit or the second logic circuit. 19. The circuit of claim 18, wherein the number of pipeline stages in the pipelined routing path is less than the number of pipeline stages in the at least one of the first logic circuit or the second logic circuit. 20. The integrated circuit of claim 17, wherein the integrated circuit comprises a programmable logic device (PLD).