초록 ▼

An output circuit having an output transistor which switches a load current is disclosed. The output circuit includes a load current detecting block which detects a current level of the load current, and a slew rate adjustment block which adjusts a slew rate during a turn-off transition of the outpu

An output circuit having an output transistor which switches a load current is disclosed. The output circuit includes a load current detecting block which detects a current level of the load current, and a slew rate adjustment block which adjusts a slew rate during a turn-off transition of the output transistor in response to a result of the detection by the load current detecting block.

대표청구항 ▼

What is claimed is: 1. An output circuit, comprising: an output transistor supplying a load current to a load; a control signal input circuit supplying a switching signal to turn on/off the output transistor in response to an external switching signal applied to the control signal input circuit; a

What is claimed is: 1. An output circuit, comprising: an output transistor supplying a load current to a load; a control signal input circuit supplying a switching signal to turn on/off the output transistor in response to an external switching signal applied to the control signal input circuit; a load current detecting block detecting a current level of a current flowing through the output transistor; a first off-rate adjustment circuit coupled between a gate terminal and a source terminal of the output transistor and including a depression-type MOS transistor, the depression-type MOS transistor having a gate terminal coupled with a first output terminal of the load current detecting block; and a second off-rate adjustment circuit coupled between the gate terminal and the source terminal of the output transistor and including an enhancement-type MOS transistor, the enhancement-type MOS transistor having a gate terminal coupled with a second output terminal of the load current detecting block, wherein the load current detecting block outputs a first activation signal, which is dependent on the switching signal to turn off the output transistor, at the first output terminal to turn on the depression-type MOS transistor when the load current detecting block detects a first current level flows through the output transistor, and the load current detecting block outputs a second activation signal, which is independent from the external switching signal, to the second output terminal to turn on the enhancement-type MOS transistor when the load current detecting block detects a second current level larger than the first current level flows through the output transistor. 2. The output circuit according to claim 1, wherein the control signal input circuit supplies the switching signal to the load current detecting block in response to the external switching signal. 3. The output circuit according to claim 2, wherein the load current detecting block supplies an OFF-signal to the control signal input circuit when the load current detecting block detects the second current level, the control signal input circuit changes the switching signal to turn off the output transistor even when the external switching signal indicates a state to turn on the output transistor. 4. The output circuit according to claim 1, wherein the first off-rate adjustment circuit further includes a resistor connected in series with the depression-type MOS transistor. 5. The output circuit according to claim 1, wherein a drain terminal of the output transistor is connected to a power source terminal, and the source terminal of the output transistor is connected to an output terminal for connecting with the load. 6. The output circuit according to claim 5, further comprising: a boost circuit coupled between the control signal input circuit and the gate terminal of the output transistor, the boost circuit outputting a boosted voltage higher than a voltage of the power source terminal in response to the switching signal to turn on the output transistor. 7. The output circuit according to claim 6, further comprising a rise-rate adjustment resistor coupled between the boost circuit and the gate terminal of the output transistor. 8. The output circuit according to claim 7, wherein the first and second off-rate adjustment circuits are coupled between a node between the rise-rate adjustment resistor and the gate terminal of the output transistor and the source terminal of the output transistor. 9. The output circuit according to claim 1, wherein the depression-type MOS transistor is defined as a first depression-type MOS transistor, the output circuit further comprising: a third off-rate adjustment circuit coupled between the gate terminal and the source terminal of the output transistor and including a second depression-type MOS transistor, the second depression-type MOS transistor having a gate terminal coupled with a third output terminal of the load current detecting block, wherein the load current detecting block outputs a third activation signal to the third output terminal to turn on the second depression-type MOS transistor when the load current detecting block detects a third current level larger than the first current level and smaller than the second current level flows through the output transistor. 10. The output circuit according to claim 9, wherein the resistor in the first off-rate adjustment circuit is defined as a first resistor, the third off-rate adjustment circuit further includes a second resistor connected in series with the second depression-type MOS transistor. 11. The output circuit according to claim 9, further comprising: a boost circuit coupled between the control signal input circuit and the gate terminal of the output transistor, the boost circuit outputting a boosted voltage higher than a voltage of the power source terminal in response to the switching signal to turn on the output transistor; and a rise-rate adjustment resistor coupled between the boost circuit and the gate terminal of the output transistor, wherein the first to third off-rate adjustment circuits are coupled between a node between the rise-rate adjustment resistor and the gate terminal of the output transistor and the source terminal of the output transistor.