IPC분류정보
| 국가/구분 |
United States(US) Patent
등록
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| 국제특허분류(IPC7판) |
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| 출원번호 |
UP-0643742
(2003-08-18)
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| 등록번호 |
US-7743223
(2010-07-12)
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발명자
/ 주소 |
- Scott, Steven L.
- Faanes, Gregory J.
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| 출원인 / 주소 |
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| 대리인 / 주소 |
Schwegman, Lundberg & Woessner, P.A.
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| 인용정보 |
피인용 횟수 :
0 인용 특허 :
84 |
초록
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In a computer system having a plurality of processors connected to a shared memory, a system and method of decoupling an address from write data in a store to the shared memory. A write request address is generated for a memory write, wherein the write request address points to a memory location in
In a computer system having a plurality of processors connected to a shared memory, a system and method of decoupling an address from write data in a store to the shared memory. A write request address is generated for a memory write, wherein the write request address points to a memory location in shared memory. A write request is issued to the shared memory, wherein the write request includes the write request address. The write request address is noted in the shared memory and addresses in subsequent load and store requests are compared in share memory to the write request address. The write data is transferred to the shared memory and matched, within the shared memory, to the write request address. The write data is then stored into the shared memory as a function of the write request address.
대표청구항
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What is claimed is: 1. In a computer system having a plurality of processors connected to across a network a shared memory, a method of decoupling a write address from its corresponding write data in a store to the shared memory, comprising: generating a write request address for a memory write, wh
What is claimed is: 1. In a computer system having a plurality of processors connected to across a network a shared memory, a method of decoupling a write address from its corresponding write data in a store to the shared memory, comprising: generating a write request address for a memory write, wherein the write request address points to a memory location in the shared memory; transferring a write request to the shared memory, wherein the write request includes the write request address; noting the write request address in the shared memory; enforcing memory ordering in subsequent load and store requests to the write request address until the write data associated with the write request is written into the shared memory; when the corresponding write data becomes available, transferring the write data to the shared memory in instruction order across the network without the write request address; pairing, within the shared memory, the write request address with the separately transferred corresponding write data; and storing the write data into the shared memory as a function of the write request address. 2. The method according to claim 1, wherein the shared memory includes a store address buffer and wherein noting the write request address includes writing the address in the store address buffer. 3. The method according to claim 2, further comprising comparing, in the shared memory, addresses in the subsequent load and store requests to the write request address, wherein comparing addresses in the subsequent load and store requests includes stalling the subsequent load requests to the write request address until the write data is written into the shared memory if there is a match. 4. The method according to claim 1, further comprising comparing, in the shared memory, addresses in the subsequent load and store request to the write request address, wherein the shared memory includes a cache, wherein noting the write request address includes changing a state in a cache line associated with the write request address to “WaitForData”, and wherein comparing addresses in subsequent load and store requests to the write request address includes accessing the cache and stalling if a cache line hit returns a “WaitForData” state. 5. The method according to claim 1, further comprising comparing, in the shared memory, addresses in the subsequent load and store request to the write request address, wherein the shared memory includes a bit vector, wherein noting the write request address in the shared memory includes setting one or more bits in the bit vector corresponding to the write request address, and wherein comparing addresses in subsequent load and store requests to the write request address includes comparing bits that would be set corresponding to the load and store request addresses with the bits set for the write request address and stalling servicing of the load and store requests if there is a match. 6. The method according to claim 1, further comprising comparing, in the shared memory, addresses in the subsequent load and store request to the write request address, wherein comparing addresses in the subsequent load and store requests includes stalling the subsequent load requests to the write request address until the write data is written into the shared memory if there is a match. 7. The method according to claim 6, wherein comparing addresses in the subsequent load and store requests includes servicing the load and store requests to addresses other than the write request address without waiting for the write data to be written to the write request address if there is no match. 8. The method according to claim 1, further comprising comparing, in the shared memory, addresses in the subsequent load and store request to the write request address, wherein comparing addresses in the subsequent load and store requests includes servicing the load and store requests to addresses other than the write request address without waiting for the write data to be written to the write request address if there is no match. 9. The method according to claim 1, wherein transferring a write request includes ensuring that all vector and scalar loads from shared memory for that processor have been sent to the shared memory prior to issuing the write request. 10. A computer system, comprising: a plurality of processors, wherein the processors includes means for issuing a write address separate from data to be written to the write address; and a shared memory connected by a network to the plurality of processors, wherein the shared memory includes: means for receiving a first write request including a first write address; means for noting the write request address to the shared memory; means for stalling subsequent load and store requests to a memory location in the shared memory associated with the first write address until the data associated with the first write request is received and written by the shared memory; means for receiving write data in instruction order across the network without the write request address; and means for pairing the write request address with the separately transferred corresponding write data prior to storing the write data to the shared memory as a function of the write request address; wherein the processors enforce memory ordering in the subsequent load and store requests to the write request address until the write data associated with the first write request is written into the shared memory. 11. In a computer system having a plurality of processors connected to a shared memory, a method of decoupling a write address from its corresponding write data in a write to the shared memory, comprising: generating a write request address for a memory write, wherein the write request address points to a memory location in shared memory; issuing a first write request to the shared memory, wherein the first write request includes the write request address; noting the write request address in the shared memory; comparing, in the shared memory, addresses in subsequent read and write requests to the write request address; stalling the subsequent read requests to the write request address until the write data corresponding to the first write request is written into the shared memory; and if the address in a subsequent write request matches the write request address stored in the shared memory and there are no stalled read requests to the write request address, discarding the first write request. 12. The method according to claim 11, wherein the shared memory includes a store address buffer and wherein noting the write request address includes writing the address in the store address buffer. 13. The method according to claim 12, wherein comparing addresses in subsequent read and write requests includes stalling subsequent read requests to the write request address until the write data is written into the shared memory. 14. The method according to claim 11, wherein the shared memory includes a cache, wherein noting the write request address includes changing a state in a cache line associated with the write request address to “WaitForData”, and wherein comparing addresses in subsequent read and write requests to the write request address includes accessing the cache and stalling if a cache line hit returns a “WaitForData” state. 15. The method according to claim 11, wherein the shared memory includes a bit vector, wherein noting the write request address in the shared memory includes setting one or more bits in the bit vector corresponding to the write request address, and wherein comparing addresses in subsequent read and write requests to the write request address includes comparing bits that would be set corresponding to the load and store request addresses the bits set for the write request address and stalling servicing of the load and store requests if there is a match. 16. The method according to claim 11, wherein comparing addresses in subsequent read and write requests includes stalling the subsequent read requests to the write request address until the write data is written into the shared memory. 17. The method according to claim 16, wherein comparing addresses in subsequent read and write requests includes servicing the read and write requests to addresses other than the write request address without waiting for the write data to be written to the write request address. 18. The method according to claim 11, wherein comparing addresses in subsequent read and write requests includes servicing the read and write requests to addresses other than the write request address without waiting for the write data to be written to the write request address. 19. The method according to claim 11, wherein comparing addresses in subsequent read and write requests includes enforcing memory ordering in the subsequent read and write requests to the write request address until the write data associated with the first write request is written into the shared memory. 20. The method according to claim 11, wherein issuing a write request includes ensuring that all vector and scalar loads from shared memory for that processor have been sent to the shared memory prior to issuing the write request. 21. In a computer system having a plurality of processors connected across a network to a shared memory, a method of decoupling a write address from its corresponding write data in a store to the shared memory, comprising: generating a write request address for a vector store to memory, wherein the write request address points to a memory location in the shared memory; transferring a vector store request to the shared memory, wherein the write request includes the write request address; noting the write request address to the shared memory; enforcing memory ordering in subsequent load and store requests to the write request address until the write data associated with the write request is written into the shared memory; when the corresponding write data becomes available, transferring the write data from a vector register to the shared memory in instruction order across the network without the write request address; pairing, within the shared memory, the write request address with the separately transferred corresponding write data; and storing the write data into the shared memory as a function of the write request address. 22. The method according to claim 21, wherein the shared memory includes a store address buffer and wherein noting the write request address includes writing the address in the store address buffer. 23. The method according to claim 22, further comprising comparing, in the shared memory, addresses in the subsequent load and store requests to the write request address, wherein comparing addresses in the subsequent load and store requests includes stalling the subsequent load requests to the write request address until the write data is written into the shared memory if there is a match. 24. The method according to claim 21, further comprising comparing, in the shared memory, addresses in the subsquent load and store requests to the write request address, wherein the shared memory includes a cache, wherein noting the write request address includes changing a state in a cache line associated with the write request address to “WaitForData”, and wherein comparing addresses in the subsequent load and store requests to the write request address includes accessing the cache and stalling if a cache line hit returns a “WaitForData” state. 25. The method according to claim 21, further comprising comparing, in the shared memory, addresses in the subsequent load and store requests to the write request address, wherein the shared memory includes a bit vector, wherein noting the write request address in the shared memory includes setting one or more bits in the bit vector corresponding to the write request address, and wherein comparing addresses in the subsequent load and store requests to the write request address includes comparing bits that would be set corresponding to the load and store request addresses with the bits set for the write request address and stalling servicing of the load and store requests if there is a match. 26. The method according to claim 21, further comprising comparing, in the shared memory, addresses in the subsequent load and store requests to the write request address, wherein comparing addresses in the subsequent load and store requests includes stalling the subsequent load requests to the write request address until the write data is written into the shared memory if there is a match. 27. The method according to claim 26, wherein comparing addresses in the subsequent load and store requests includes servicing the load and store requests to addresses other than the write request address without waiting for the write data to be written to the write request address if there is no match. 28. The method according to claim 21, further comprising comparing, in the shared memory, addresses in the subsequent load and store requests to the write request address, wherein comparing addresses in the subsequent load and store requests includes servicing the load and store requests to addresses other than the write request address without waiting for the write data to be written to the write request address if there is no match. 29. The method according to claim 21, wherein transferring a write request includes ensuring that all vector and scalar loads from shared memory for that processor have been sent to the shared memory prior to issuing the write request. 30. A method of decoupling vector data stores from vector instruction execution, comprising: executing a vector instruction on vector data stored in a vector register, wherein executing a vector instruction includes storing result vector data in the vector register; generating a vector write address for a vector store; transferring a vector store request across a network to memory, wherein the vector store request includes the vector write address; noting the vector write address in the memory; enforcing memory ordering in subsequent read and write requests to the vector write address until the result vector data associated with the vector store request is written into the memory; when the corresponding write data becomes available, transferring the result vector data from the vector register to the memory in instruction order across the network without the vector write address; pairing, within the memory, the vector write address with the separately transferred corresponding result vector data; and storing the result vector data into the memory as a function of the vector write address in the vector store request. 31. The method according to claim 30, further comprising comparing, in the memory, addresses in the subsequent read and write requests to the vector write request address, wherein comparing addresses in the subsequent read and write requests to the vector write address includes stalling the subsequent read requests to the vector write address until the result vector data is written into the memory. request is received and written by the shared memory. 32. In a processor having a plurality of processing units connected across a network to a shared memory, a method of decoupling a write address from its corresponding write data in a write to the shared memory, comprising: generating a write request address for a memory write, wherein the write request address points to a memory location in the shared memory; transferring a write request to the shared memory, wherein the write request includes the write request address; storing the write request address in the shared memory; enforcing memory ordering in the subsequent read and write requests to the write request address until the write data associated with the request is written into the shared memory; when the corresponding write data becomes available, transferring the write data to the shared memory in instruction order across the network without the write request address; pairing, within the shared memory, the write request address with the separately transferred corresponding write data; and storing the corresponding write data into the shared memory as a function of the write request address. 33. The method according to claim 32, wherein transferring a write request includes ensuring that all vector and scalar loads from shared memory for that processor have been sent to the shared memory prior to issuing the write request. 34. The method according to claim 32, further comprising comparing, in the shared memory, addresses in the subsequent read and write requests to the write request address, wherein comparing addresses in the subsequent read and write requests includes stalling the subsequent read requests to the write request address until the write data is written into the shared memory if there is a match. 35. The method according to claim 34, wherein comparing addresses in the subsequent read and write requests includes servicing the read and write requests to addresses other than the write request address without waiting for the write data to be written to the request address if there is no match.
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