IPC분류정보
국가/구분 |
United States(US) Patent
등록
|
국제특허분류(IPC7판) |
|
출원번호 |
UP-0417024
(2009-04-02)
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등록번호 |
US-7746104
(2010-07-19)
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발명자
/ 주소 |
- Gaide, Brian C.
- Young, Steven P.
|
출원인 / 주소 |
|
대리인 / 주소 |
|
인용정보 |
피인용 횟수 :
4 인용 특허 :
21 |
초록
▼
A programmable integrated circuit includes a plurality of interconnected logic blocks, each including a logic circuit and an output multiplexer circuit. The output multiplexer circuit includes a first multiplexer having first and second data inputs respectively coupled to first and second outputs of
A programmable integrated circuit includes a plurality of interconnected logic blocks, each including a logic circuit and an output multiplexer circuit. The output multiplexer circuit includes a first multiplexer having first and second data inputs respectively coupled to first and second outputs of the logic circuit, a select input coupled to an output of another logic block, and a first data output. A second output multiplexer may also have first and second data inputs respectively coupled to the first and second outputs of the logic circuit, a select input coupled to the output of the another logic block, and a second data output. The output multiplexer circuit is programmably coupled, in one of a plurality of operating modes, to provide an output token with the first output of each logic block only when the output multiplexer circuit of the logic block receives tokens indicating valid new data on each of the first, second, and select inputs of the circuit.
대표청구항
▼
What is claimed is: 1. A programmable integrated circuit, comprising: a plurality of interconnected logic blocks, each of the logic blocks comprising: a logic circuit; and an output multiplexer circuit comprising a first multiplexer having first and second data inputs respectively coupled to first
What is claimed is: 1. A programmable integrated circuit, comprising: a plurality of interconnected logic blocks, each of the logic blocks comprising: a logic circuit; and an output multiplexer circuit comprising a first multiplexer having first and second data inputs respectively coupled to first and second outputs of the logic circuit, a select input coupled to an output of another of the logic blocks, and a data output coupled to a first output of the logic block, wherein the output multiplexer circuit is programmably coupled, in one of a plurality of operating modes of the output multiplexer circuit, to provide an output token with the first output of each logic block only when the output multiplexer circuit of the logic block receives tokens indicating valid new data on each of the first data input, the second data input, and the select input of the output multiplexer circuit. 2. The programmable integrated circuit of claim 1, wherein the plurality of logic blocks comprises an array of the logic blocks, and the logic blocks are substantially similar one to another. 3. The programmable integrated circuit of claim 2, wherein for each logic block the select input is coupled to a select output of an output multiplexer circuit in an adjacent logic block in the array. 4. The programmable integrated circuit of claim 1, wherein each output multiplexer circuit further comprises a select multiplexer coupled between the another of the logic blocks and the first multiplexer, the select multiplexer having a first data input coupled to the output of the another of the logic blocks and a data output coupled to the select input of the first multiplexer. 5. The programmable integrated circuit of claim 1, wherein each of the output multiplexer circuits further comprises a second multiplexer having first and second data inputs respectively coupled to first and second outputs of the logic circuit, a select input coupled to the output of the another of the logic blocks, and a data output coupled to a second output of the logic block. 6. The programmable integrated circuit of claim 1, wherein the first and second data inputs of the output multiplexer circuit and the data output of the output multiplexer circuit each comprise an N-bit bus, N being an integer greater than one. 7. A programmable integrated circuit, comprising: a plurality of logic blocks; and an interconnect structure coupled between the logic blocks, wherein each of the logic blocks comprises: a logic circuit having inputs coupled to the interconnect structure and further having first and second outputs; and an output multiplexer circuit having first and second data inputs coupled to the first and second outputs of the logic circuit and further having a data output coupled to the interconnect structure, wherein each output multiplexer circuit is programmably coupled, in one of a plurality of operating modes of the output multiplexer circuit, to output a result of implementing a first multiplexing function between the first and second data inputs; and wherein the first multiplexing function in each output multiplexer circuit is controlled by a select input comprising a dynamic signal. 8. The programmable integrated circuit of claim 7, wherein each output multiplexer circuit is further programmably coupled, in the one of the operating modes, to provide an output token with the result only when the output multiplexer circuit receives tokens indicating valid new data on each of the first data input, the second data input, and the select input. 9. The programmable integrated circuit of claim 7, wherein: the plurality of logic blocks comprises an array of the logic blocks; the logic blocks are substantially similar one to another; and for each logic block the select input is coupled to a select output of an adjacent logic block in the array. 10. The programmable integrated circuit of claim 9, wherein for each logic block the select input is coupled to a select output of an output multiplexer circuit in the adjacent logic block. 11. The programmable integrated circuit of claim 7, wherein each output multiplexer circuit further comprises: a select multiplexer having a first data input coupled to receive the dynamic signal, a second data input, and a data output coupled to control the first multiplexing function. 12. The programmable integrated circuit of claim 7, wherein: each output multiplexer circuit is further programmably coupled, in the one of the operating modes, to output a second value comprising a result of implementing a second multiplexing function between the first and second data inputs; and for each output multiplexer circuit, the second multiplexing function is controlled by the select input. 13. The programmable integrated circuit of claim 7, wherein the first and second data inputs and the output of the output multiplexer circuit each comprise an N-bit bus, N being an integer greater than one, and the dynamic signal on the select input comprises a single-bit value. 14. A programmable integrated circuit, comprising: an array of substantially similar programmable logic blocks; and an interconnect structure coupled between the programmable logic blocks, wherein each of the programmable logic blocks comprises: a logic circuit having inputs coupled to the interconnect structure and further having first and second outputs; and an output multiplexer circuit having first and second data inputs coupled to the first and second outputs of the logic circuit and further having a data output coupled to the interconnect structure, wherein each output multiplexer circuit is programmably coupled to output a result of implementing a first multiplexing function between the first and second data inputs, and wherein the first multiplexing function in each output multiplexer circuit is controlled by a select input comprising a dynamic signal. 15. The programmable integrated circuit of claim 14, wherein the output multiplexer circuit is programmably coupled to provide an output token with the result only when the output multiplexer circuit receives tokens indicating valid new data on the first data input, the second data input, and the select input. 16. The programmable integrated circuit of claim 14, wherein for each programmable logic block the select input is programmably coupled to a select output of an adjacent programmable logic block in the array. 17. The programmable integrated circuit of claim 16, wherein for each programmable logic block the select input is programmably coupled to a select output of an output multiplexer circuit in the adjacent programmable logic block. 18. The programmable integrated circuit of claim 14, wherein each output multiplexer circuit further comprises: a programmable select multiplexer having a first data input coupled to receive the dynamic signal, a second data input, and a data output coupled to control the first multiplexing function. 19. The programmable integrated circuit of claim 14, wherein each output multiplexer circuit is further programmably coupled to output a second value comprising a result of implementing a second multiplexing function between the first and second data inputs. 20. The programmable integrated circuit of claim 14, wherein the first and second data inputs of the output multiplexer circuit and the data output of the output multiplexer circuit each comprise an N-bit bus, N being an integer greater than one.
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