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Circuits for merging data streams in a self-timed programmable integrated circuit. A programmable integrated circuit includes interconnected logic blocks, each including a logic circuit and an output multiplexer circuit including an arbiter and a multiplexer. Each arbiter is coupled to receive ready

Circuits for merging data streams in a self-timed programmable integrated circuit. A programmable integrated circuit includes interconnected logic blocks, each including a logic circuit and an output multiplexer circuit including an arbiter and a multiplexer. Each arbiter is coupled to receive ready signals provided with first and second outputs of the logic circuit. Each multiplexer has first and second data inputs coupled to the outputs of the logic circuit, a select input programmably coupled, in one of a plurality of operating modes, to an arbiter output, and a data output coupled to an output of the logic block. The output multiplexer circuit provides an output token only when a first token indicates valid new data on the arbiter output and a second token indicates valid new data on one of the data inputs, and stores a third token received on the other data input until the other data input is selected by the multiplexer.

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What is claimed is: 1. A programmable integrated circuit, comprising: a plurality of interconnected logic blocks, each of the logic blocks comprising: a logic circuit having an input coupled to an input of the logic block, and further having first and second outputs; and an output multiplexer circu

What is claimed is: 1. A programmable integrated circuit, comprising: a plurality of interconnected logic blocks, each of the logic blocks comprising: a logic circuit having an input coupled to an input of the logic block, and further having first and second outputs; and an output multiplexer circuit comprising an arbiter coupled to receive ready signals provided with the first and second outputs of the logic circuit, and a first multiplexer having first and second data inputs respectively coupled to the first and second outputs of the logic circuit, a select input programmably coupled, in one of a plurality of operating modes of the output multiplexer circuit, to an output of the arbiter, and a data output coupled to a first output of the logic block. 2. The programmable integrated circuit of claim 1, wherein: the output multiplexer circuit is programmably coupled, when in the one of the operating modes of the output multiplexer circuit, to provide an output token with the first output of each logic block only when a first token indicates valid new data on the arbiter output and a second token indicates valid new data on a first one of the first or second data inputs; and the output multiplexer circuit is further programmably coupled, when in the one of the operating modes of the output multiplexer circuit, to store a third token received on a second one of the first or second data inputs until the second one of the first or second data inputs is selected by the select input of the first multiplexer. 3. The programmable integrated circuit of claim 1, wherein the plurality of interconnected logic blocks comprises an array of the logic blocks, and the logic blocks are substantially similar one to another. 4. The programmable integrated circuit of claim 1, wherein the ready signals comprise handshake signals in handshake logic operating in 2-phase mode. 5. The programmable integrated circuit of claim 1, wherein each of the output multiplexer circuits further comprises a second multiplexer having first and second data inputs respectively coupled to the first and second outputs of the logic circuit, a select input coupled to the output of the arbiter, and a data output coupled to a second output of the logic block. 6. The programmable integrated circuit of claim 1, wherein the first and second data inputs of the first multiplexer and the data output of the first multiplexer each comprise an N-bit bus, N being an integer greater than one. 7. The programmable integrated circuit of claim 1, wherein the programmable integrated circuit comprises a programmable logic device (PLD). 8. A programmable integrated circuit, comprising: a plurality of logic blocks; and an interconnect structure coupled between the logic blocks, wherein each of the logic blocks comprises: a logic circuit having inputs coupled to the interconnect structure and further having first and second outputs; means for programming the logic block to operate in one of a plurality of operating modes; and means for merging, when operating in the one of the operating modes, a self-timed first data stream on the first output of the logic circuit with a self-timed second data stream on the second output of the logic circuit to form a self-timed merged data stream, the means for merging having first and second data inputs respectively coupled to the first and second outputs of the logic circuit, and a data output coupled to a self-timed first output of the logic block. 9. The programmable integrated circuit of claim 8, wherein in each logic block the means for merging comprises: an arbiter coupled to receive ready signals provided with the first and second outputs of the logic circuit, and a first multiplexer having first and second data inputs respectively coupled to the first and second outputs of the logic circuit, a select input programmably coupled, when in the one of the operating modes of the output multiplexer circuit, to an output of the arbiter, and a data output coupled to the first output of the logic block. 10. The programmable integrated circuit of claim 9, wherein in each logic block the means for merging further comprises a second multiplexer having first and second data inputs respectively coupled to the first and second outputs of the logic circuit, a select input coupled to the output of the arbiter, and a data output coupled to a second output of the logic block. 11. The programmable integrated circuit of claim 9, wherein the ready signals comprise handshake signals in handshake logic operating in 2-phase mode. 12. The programmable integrated circuit of claim 9, wherein the first and second data inputs and the data output of the first multiplexer each comprise an N-bit bus, N being an integer greater than one, and the output of the arbiter comprises a self-timed single-bit value. 13. The programmable integrated circuit of claim 8, wherein: the means for merging is programmably coupled, when operating in the one of the operating modes, to provide an output token with the first output of each logic block only when a first token indicates valid new data on the arbiter output and a second token indicates valid new data on a first one of the first or second data inputs; and the means for merging is further programmably coupled, when operating in the one of the operating modes, to store a third token received on a second one of the first or second data inputs until the second one of the first or second data inputs is selected by the select input of the first multiplexer. 14. The programmable integrated circuit of claim 8, wherein the plurality of logic blocks comprises an array of the logic blocks, and the logic blocks are substantially similar one to another. 15. A programmable integrated circuit, comprising: an array of substantially similar programmable logic blocks; and an interconnect structure coupled between the programmable logic blocks, wherein each of the programmable logic blocks comprises: a programmable logic circuit having inputs coupled to the interconnect structure and further having first and second outputs; and an output multiplexer circuit comprising an arbiter coupled to receive ready signals provided with the first and second outputs of the programmable logic circuit, and a first multiplexer having first and second data inputs respectively coupled to the first and second outputs of the logic circuit, a select input programmably coupled, in one of a plurality of operating modes of the output multiplexer circuit, to an output of the arbiter, and a data output coupled to a first output of the programmable logic block. 16. The programmable integrated circuit of claim 15, wherein: the output multiplexer circuit is programmably coupled, when operating in the one of the operating modes, to provide an output token with the first output of each logic block only when a first token indicates valid new data on the arbiter output and a second token indicates valid new data on a first one of the first or second data inputs; and the output multiplexer circuit is further programmably coupled, when operating in the one of the operating modes, to store a third token received on a second one of the first or second data inputs until the second one of the first or second data inputs is selected by the select input of the first multiplexer. 17. The programmable integrated circuit of claim 15, wherein the ready signals comprise handshake signals in handshake logic operating in 2-phase mode. 18. The programmable integrated circuit of claim 15, wherein each of the output multiplexer circuits further comprises a second multiplexer having first and second data inputs respectively coupled to the first and second outputs of the logic circuit, a select input coupled to the output of the arbiter, and a data output coupled to a second output of the programmable logic block. 19. The programmable integrated circuit of claim 15, wherein the first and second data inputs and the data output of the first multiplexer each comprise an N-bit bus, N being an integer greater than one, and the output of the arbiter comprises a self-timed single-bit value. 20. The programmable integrated circuit of claim 15, wherein the programmable integrated circuit comprises a programmable logic device (PLD).