Compute-centric architecture for integrated circuits
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
G06F-007/38
H03K-019/177
출원번호
UP-0417013
(2009-04-02)
등록번호
US-7746108
(2010-07-19)
발명자
/ 주소
Young, Steven P.
Gaide, Brian C.
출원인 / 주소
Xilinx, Inc.
대리인 / 주소
Cartier, Lois D.
인용정보
피인용 횟수 :
6인용 특허 :
43
초록▼
Integrated circuits having a compute-centric architecture. An integrated circuit may include an array of interconnected substantially similar logic blocks, each including a multiplier circuit and a lookup table circuit. The multiplier circuit has first and second inputs coupled to first and second d
Integrated circuits having a compute-centric architecture. An integrated circuit may include an array of interconnected substantially similar logic blocks, each including a multiplier circuit and a lookup table circuit. The multiplier circuit has first and second inputs coupled to first and second data inputs of the logic block, and an output, and may include a non-uniform array of sub-circuits. The lookup table circuit has a first input coupled to a third data input of the logic block, a second input coupled to the output of the multiplier circuit, and an output coupled to a data output of the logic block. The multiplier circuits in adjacent logic blocks may be coupled together via a multi-bit partial product bus. Optional storage elements store the first and second inputs and the output of the multiplier circuit, the partial product bus, and the output of the lookup table circuit.
대표청구항▼
What is claimed is: 1. An integrated circuit, comprising: an array of interconnected substantially similar logic blocks, wherein each logic block comprises: a multiplier circuit having first and second inputs coupled to first and second data inputs of the logic block, and further having an output,
What is claimed is: 1. An integrated circuit, comprising: an array of interconnected substantially similar logic blocks, wherein each logic block comprises: a multiplier circuit having first and second inputs coupled to first and second data inputs of the logic block, and further having an output, the multiplier circuit comprising a non-uniform array of sub-circuits; and a lookup table circuit having a first input coupled to a third data input of the logic block, a second input coupled to the output of the multiplier circuit, and an output coupled to a data output of the logic block. 2. The integrated circuit of claim 1, wherein each of the multiply blocks comprises: a plurality of logical AND gates; and a plurality of full adder circuits, each of the full adder circuits having an input coupled to an output of a corresponding one of the logical AND gates. 3. The integrated circuit of claim 1, wherein each of the multiply blocks comprises M rows and N columns of sub-circuits, M and N being integers greater than one. 4. The integrated circuit of claim 3, wherein M and N are both equal to eight. 5. The integrated circuit of claim 3, wherein in each multiply block, N−1 columns of the sub-circuits comprise logical AND gates and full adder circuits, and one column of the sub-circuits comprises logical AND gates and omits the full adder circuits. 6. The integrated circuit of claim 1, wherein the lookup table circuit comprises: a first lookup table (LUT) having a first input coupled to the third data input of the logic block, a second input coupled to the output of the multiplier circuit, and an output; and a second LUT having a first input coupled to the output of the first LUT, a second input coupled to a carry in input of the logic block, and an output coupled to the data output of the logic block. 7. The integrated circuit of claim 6, wherein the lookup table circuit further comprises: a carry multiplexer having a first data input coupled to the carry in input of the logic block, a second data input coupled to the output of the multiplier circuit, a select input coupled to the output of the first LUT, and an output coupled to a carry out output of the logic block. 8. The integrated circuit of claim 1, wherein the multiplier circuits in adjacent logic blocks are coupled together via a multi-bit partial product bus. 9. The integrated circuit of claim 8, wherein: each of the multiplier circuits includes a plurality of first storage elements coupled to store the first and second inputs of the multiplier circuit, the output of the multiplier circuit, and the partial product bus; and each of the lookup table circuits includes a second storage element coupled to store the output of the lookup table circuit. 10. The integrated circuit of claim 9, wherein the first and second storage elements comprise latches. 11. An integrated circuit, comprising: an array of interconnected substantially similar bus-based logic blocks, wherein each logic block comprises: a multiplier circuit having multi-bit first and second inputs coupled to multi-bit first and second data inputs of the logic block, and further having a multi-bit output; and a multi-bit lookup table circuit having a multi-bit first input coupled to a multi-bit third data input of the logic block, a multi-bit second input coupled to the output of the multiplier circuit, and a multi-bit output coupled to a multi-bit data output of the logic block. 12. The integrated circuit of claim 11, wherein each of the multiply blocks comprises: a plurality of logical AND gates; and a plurality of full adder circuits, each of the full adder circuits having an input coupled to an output of a corresponding one of the logical AND gates. 13. The integrated circuit of claim 11, wherein each of the multiply blocks comprises M rows and N columns of sub-circuits, M and N being integers greater than one. 14. The integrated circuit of claim 13, wherein M and N are both equal to eight. 15. The integrated circuit of claim 13, wherein in each multiply block, N−1 columns of the sub-circuits comprise logical AND gates and full adder circuits, and one column of the sub-circuits comprises logical AND gates and omits the full adder circuits. 16. The integrated circuit of claim 11, wherein in each logic block, the lookup table circuit comprises: a first plurality of lookup tables (LUTs) having a multi-bit first input coupled to the third data input of the logic block, a multi-bit second input coupled to the output of the multiplier circuit, and a multi-bit output; and a second plurality of LUTs having a multi-bit first input coupled to the output of the first plurality of LUTs, a second input coupled to a carry chain of the logic block, and a multi-bit output coupled to the data output of the logic block. 17. The integrated circuit of claim 16, wherein in each logic block, the lookup table circuit further comprises: a plurality of carry multiplexers coupled in series, each carry multiplexer having a first data input coupled to a carry out signal from a preceding carry multiplexer and further coupled to the second input of a corresponding one of the second plurality of LUTs, a second data input coupled to a corresponding bit of the output of the multiplier circuit, a select input coupled to a corresponding bit of the output of the first plurality of LUTs, and an output coupled to a carry in input of a successive carry multiplexer. 18. The integrated circuit of claim 11, wherein the multiplier circuit in each logic block comprises a multiply block coupled to multiply blocks in adjacent logic blocks via a multi-bit partial product bus. 19. The integrated circuit of claim 18, wherein: each of the multiplier circuits includes a plurality of multi-bit first storage elements coupled to store the first and second inputs of the multiplier circuit, the output of the multiplier circuit, and the partial product bus; and each of the lookup table circuits includes a multi-bit second storage element coupled to store the output of the lookup table circuit. 20. The integrated circuit of claim 19, wherein each of the first and second storage elements comprises a plurality of latches.
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