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Circuits for sharing self-timed logic

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-007/38
  • H03K-019/177
출원번호 UP-0417054 (2009-04-02)
등록번호 US-7746109 (2010-07-19)
발명자 / 주소
  • Young, Steven P.
  • Gaide, Brian C.
출원인 / 주소
  • Xilinx, Inc.
대리인 / 주소
    Cartier, Lois D.
인용정보 피인용 횟수 : 6  인용 특허 : 44

초록

An exemplary circuit for implementing logic sharing in self-timed circuits includes a shared logic circuit, an input circuit, an output circuit, and a pipelined routing path. The shared logic circuit has first and second self-timed inputs and first and second self-timed outputs. The input circuit is

대표청구항

What is claimed is: 1. A circuit, comprising: a shared logic circuit having first and second self-timed inputs and first and second self-timed outputs; an input circuit coupled to output a selected one of the first or second self-timed inputs to the shared logic circuit, the selected one of the fir

이 특허에 인용된 특허 (44)

  1. Simkins,James M.; Young,Steven P.; Wong,Jennifer; New,Bernard J.; Ching,Alvin Y., Arithmetic circuit with multiplexed addend inputs.
  2. Jean-Francois Hugues FR; Pascal Vivet FR, Asynchronous circuit for detecting and correcting soft error and implementation method thereof.
  3. Stuart Alexander Ridgway, Asynchronous completion prediction.
  4. Singh, Montek; Nowick, Steven M., Asynchronous pipeline with latch controllers.
  5. Cummings,Uri; Lines,Andrew, Asynchronous static random access memory.
  6. Frisch,Arnold M., Automatic skew correction for differential signals.
  7. Singh,Montek; Nowick,Steven M., Circuits and methods for high-capacity asynchronous pipeline processing.
  8. Schmit, Herman; Caldwell, Andrew; Teig, Steven, Configurable integrated circuit with a 4-to-1 multiplexer.
  9. Verma,Hare K.; Sunkavalli,Ravi; Gunwani,Manoj; Mulpuri,Chandra, Dedicated logic cells employing sequential logic and control logic functions.
  10. Ivan E. Sutherland ; Josephus C. Ebergen, Distributing data to multiple destinations within an asynchronous circuit.
  11. Fujii Koji,JPX ; Douseki Takakuni,JPX, Dynamic logic circuit and self-timed pipelined datapath system.
  12. Wittig Ralph D. ; Mohan Sundararajarao ; Carberry Richard A., FPGA configurable logic block with multi-purpose logic/memory circuit.
  13. Wittig Ralph D. ; Mohan Sundararajarao ; Carberry Richard A., FPGA configurable logic block with multi-purpose logic/memory circuit.
  14. Wittig Ralph D. ; Mohan Sundararajarao ; Carberry Richard A., FPGA configurable logic block with multi-purpose logic/memory circuit.
  15. Manohar,Rajit; Kelly,Clinton W., Fault tolerant asynchronous circuits.
  16. Manohar,Rajit; Kelly,Clinton W., Fault tolerant asynchronous circuits.
  17. Ebeling William H. C. (Seattle WA) Borriello Gaetano (Seattle WA), Field programmable gate array.
  18. Hauck Scott A. (5219 22nd Ave. NE. ; #4 Seattle WA 98105) Borriello Gaetano (8045 Bagley Ave. N. Seattle WA 98103) Burns Steven M. (6033 31st Ave. NE. Seattle WA 98115) Ebeling William H. C. (4002 Bu, Field programmable gate array for synchronous and asynchronous operation.
  19. Milshtein, Mark S.; Sprague, Milo D.; Chappell, Terry I.; Fletcher, Thomas D., Global clock self-timed circuit with self-terminating precharge for high frequency applications.
  20. Singh, Montek; Nowick, Steven M., High-throughput asynchronous dynamic pipelines.
  21. Handy James E. (San Jose CA) Maas Kelly A. (San Jose CA), Integrated cache SRAM memory having synchronous write and burst read.
  22. Bauer,Trevor J.; Young,Steven P., Integrated circuit having a programmable input structure with bounce capability.
  23. Young,Steven P.; Bauer,Trevor J., Integrated circuit having a programmable input structure with optional fanout capability.
  24. Hutchings, Brad; Redgrave, Jason, Integrated circuit with delay selecting input selection circuitry.
  25. Zeng, Richard B, Linear summation multiplier array implementation for both signed and unsigned multiplication.
  26. Chelcea, Tiberiu; Nowick, Steven M., Low latency FIFO circuits for mixed asynchronous and synchronous systems.
  27. Simkins,James M.; Young,Steven P.; Wong,Jennifer; New,Bernard J.; Ching,Alvin Y., Mathematical circuit with dynamic rounding.
  28. Nystr?m, Mika; Martin, Alain J., Method and apparatus for an asynchronous pulse logic circuit.
  29. Schleicher, James; Yuan, Richard; Pedersen, Bruce; Kaptanoglu, Sinan; Baeckler, Gregg; Lewis, David; Hutton, Mike; Lee, Andy; Saini, Rahul; Kim, Henry, Omnibus logic element.
  30. Manohar Rajit ; Martin Alain J., Parallel prefix operations in asynchronous processors.
  31. Teifel,John R.; Manohar,Rajit, Programmable asynchronous pipeline arrays.
  32. Young,Steven P.; Bauer,Trevor J.; Chirania,Manoj; Kondapalli,Venu M., Programmable logic block with dedicated and selectable lookup table outputs coupled to general interconnect structure.
  33. Simkins,James M.; Young,Steven P.; Wong,Jennifer; New,Bernard J.; Ching,Alvin Y., Programmable logic device with cascading DSP slices.
  34. Simkins,James M.; Young,Steven P.; Wong,Jennifer; New,Bernard J.; Ching,Alvin Y., Programmable logic device with pipelined DSP slices.
  35. Durham, Christopher McCall; Klim, Peter Juergen, Self-timed CMOS static logic circuit.
  36. Chren, Jr., William A., Self-timed digital processing circuits.
  37. Fujii Koji,JPX ; Douseki Takakuni,JPX, Self-timed pipelined datapath system and asynchronous signal control circuit.
  38. Fujii Koji,JPX ; Douseki Takakuni,JPX, Self-timed pipelined datapath system and asynchronous signal control circuit.
  39. Schultz,Richard; Allman,Derryl; Fure,Jan, Self-timed reliability and yield vehicle with gated data and clock.
  40. Simkins,James M.; Philofsky,Brian D., Structures and methods for implementing ternary adders/subtractors in programmable logic devices.
  41. Masteller Steven Robert, System for facilitating interfacing between multiple non-synchronous systems utilizing an asynchronous FIFO that uses asynchronous logic.
  42. Wise Adrian P.,GBX ; Dewar Kevin D.,GBX ; Jones Anthony Mark,GBX ; Sotheran Martin William,GBX ; Smith Colin,GBX ; Finch Helen Rosemary,GBX ; Claydon Anthony Peter John,GBX ; Patterson Donald William, Technique for implementing a swing buffer in a memory array.
  43. Friend,David Michael; Luick,David Arnold; Phan,Nghia Van, Wide adder with critical path of three gates.
  44. Williams Ted E. (Santa Clara County CA), Zero latency overhead self-timed iterative logic structure and method.

이 특허를 인용한 특허 (6)

  1. Parlour, David B.; Janneck, Jorn W.; Miller, Ian D., Asynchronous communication network and methods of enabling the asynchronous communication of data in an integrated circuit.
  2. Townley, Kent R.; Ebeling, Christopher D.; Fallside, Hamish; Raha, Prasun K., Clock management block.
  3. Kaviani, Alireza S., Integrated circuit and method of asynchronously routing data in an integrated circuit.
  4. Langhammer, Martin, Methods and apparatus for performing product series operations in multiplier accumulator blocks.
  5. Kaviani, Alireza S., Programmable integrated circuit and method of asynchronously routing data in a circuit block of an integrated circuit.
  6. Kaviani, Alireza S., Programmable integrated circuit and method of asynchronously routing data in an integrated circuit.
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