초록 ▼

A nonvolatile programmable logic circuit using a ferroelectric memory performs a nonvolatile memory function and an operation function without additional memory devices, thereby reducing power consumption. Also, a nonvolatile ferroelectric memory is applied to a FPGA (Field Programmable Gate Array),

A nonvolatile programmable logic circuit using a ferroelectric memory performs a nonvolatile memory function and an operation function without additional memory devices, thereby reducing power consumption. Also, a nonvolatile ferroelectric memory is applied to a FPGA (Field Programmable Gate Array), thereby preventing leakage of internal data and reducing the area of a chip.

대표청구항 ▼

The invention claimed is: 1. A nonvolatile programmable logic circuit comprising: a look-up table for selectively outputting first logic control signals outputted from a plurality of first nonvolatile ferroelectric registers in response to a logic input signal; a second nonvolatile ferroelectric re

The invention claimed is: 1. A nonvolatile programmable logic circuit comprising: a look-up table for selectively outputting first logic control signals outputted from a plurality of first nonvolatile ferroelectric registers in response to a logic input signal; a second nonvolatile ferroelectric register for outputting a second logic control signal depending on a programmed code in a nonvolatile ferroelectric capacitor; and a first transmission means for selectively transmitting an output signal from the look-up table in response to the second logic control signal, wherein each first nonvolatile ferroelectric register comprises: a pull-up driving means for driving a power voltage, wherein the pull-up driving means is connected between output terminals in a latch type configuration; a write enable control means for transmitting input data in response to a write enable signal; a storage means for generating the corresponding first logic control signal in response to a cell plate signal; a pull-down driving means for driving a ground voltage, wherein the pull-down driving means is connected between the output terminals in a latch type configuration; a pull-up means for selectively transmitting the power voltage to the pull-up driving means in response to a pull-up enable signal, wherein the power voltage is output from the pull-up driving means; and a pull-down means for selectively transmitting the ground voltage to the pull-down driving means in response to a pull-down enable signal, wherein the ground voltage is output from the pull-down driving means. 2. A circuit according to claim 1, wherein the look-up table comprises a plurality of second transmission means having a hierarchical structure for selectively transmitting corresponding signals among the first logic control signals in response to the input signals.