초록 ▼

Disclosed are moveable microstructures comprising in-plane capacitive microaccelerometers, with submicro-gravity resolution (<200 ng/√Hz) and very high sensitivity (>17 pF/g). The microstructures are fabricated in thick (>100 μm) silicon-on-insulator (SOI) substrates or s

Disclosed are moveable microstructures comprising in-plane capacitive microaccelerometers, with submicro-gravity resolution (<200 ng/√Hz) and very high sensitivity (>17 pF/g). The microstructures are fabricated in thick (>100 μm) silicon-on-insulator (SOI) substrates or silicon substrates using a two-mask fully-dry release process that provides large seismic mass (>10 milli-g), reduced capacitive gaps, and reduced in-plane stiffness. Fabricated devices may be interfaced to a high resolution switched-capacitor CMOS IC that eliminates the need for area-consuming reference capacitors. The measured sensitivity is 83 mV/mg (17 pF/g) and the output noise floor is −91 dBm/Hz at 10 Hz (corresponding to an acceleration resolution of 170 ng/√Hz). The IC consumes 6 mW power and measures 0.65 mm2 core area.

대표청구항 ▼

What is claimed is: 1. A method of fabricating a moveable microstructure, comprising: providing a substrate having upper and lower layers; etching trenches in the upper layer to define bonding pads, sense electrodes and a proof mass having capacitive gaps formed therebetween, and a plurality of tet

What is claimed is: 1. A method of fabricating a moveable microstructure, comprising: providing a substrate having upper and lower layers; etching trenches in the upper layer to define bonding pads, sense electrodes and a proof mass having capacitive gaps formed therebetween, and a plurality of tethers that allow the proof mass to move; depositing a conformal conductive layer on the substrate to reduce sizes of the capacitive gaps; etching the conformal conductive layer to remove conformal conductive material at the bottom of the trenches and provide isolation between the bonding pads and the sense electrodes; and etching the lower layer of the substrate to form a region of extra proof mass that is coupled to the proof mass formed in the upper layer. 2. The method recited in claim 1 wherein the conformal conductive layer is doped to reduce its electrical resistance. 3. The method recited in claim 1 further comprising: masking and etching the back side of the proof mass to reduce its height. 4. The method recited in claim 1 wherein the substrate comprises a silicon-on-insulator substrate. 5. The method recited in claim 1 wherein the substrate comprises a silicon substrate. 6. A method of fabricating a moveable microstructure, comprising: providing a low resistivity silicon-on-insulator substrate; etching wenches on the front side of the substrate to define bonding pads, sense electrodes and a proof mass having capacitive gaps formed therebetween; depositing a conformal conductive layer on the substrate to reduce capacitive gap sizes; doping the conformal conductive layer; etching the conformal conductive layer to remove material at the bottom of the trenches; and etching the back side of the substrate to form a region of additional proof mass and to release the microstructure. 7. The method recited in claim 6 further comprising: growing a thermal silicon oxide layer on both sides of the substrate; patterning the oxide layer on the both sides of the substrate to form an etch mask. 8. A method of fabricating a moveable microstructure, comprising: providing a silicon substrate; etching trenches on the front side of the substrate to define pads, sense electrodes and a proof mass having capacitive gaps formed therebetween; depositing a conformal conductive layer on the substrate to reduce capacitive gap sizes; bonding a handle substrate to the top side of the silicon substrate; etching the back side of the substrate to form a region of additional proof mass and to release the microstructure by etching the conformal conductive layer to remove material at the bottom of the trenches; and forming electrical connections through via holes in the handle substrate to the conformal conductive layer adjacent to pads defined in the silicon substrate. 9. The method recited in claim 8 wherein the bonded handle substrate comprises an oxidized silicon substrate.