IPC분류정보
국가/구분 |
United States(US) Patent
등록
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국제특허분류(IPC7판) |
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출원번호 |
UP-0514655
(2006-08-31)
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등록번호 |
US-7759747
(2010-08-09)
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발명자
/ 주소 |
- Forbes, Leonard
- Ahn, Kie Y.
- Bhattacharyya, Arup
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출원인 / 주소 |
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대리인 / 주소 |
Schwegman, Lundberg & Woessner, P.A.
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인용정보 |
피인용 횟수 :
8 인용 특허 :
193 |
초록
▼
Electronic apparatus and methods of forming the electronic apparatus may include a tantalum aluminum oxynitride film for use in a variety of electronic systems and devices. The tantalum aluminum oxynitride film may be structured as one or more monolayers. The tantalum aluminum oxynitride film may be
Electronic apparatus and methods of forming the electronic apparatus may include a tantalum aluminum oxynitride film for use in a variety of electronic systems and devices. The tantalum aluminum oxynitride film may be structured as one or more monolayers. The tantalum aluminum oxynitride film may be formed using atomic layer deposition. Metal electrodes may be disposed on a dielectric containing a tantalum aluminum oxynitride film.
대표청구항
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What is claimed is: 1. An integrated circuit comprising: memory, comprising flash memory, the flash memory including a plurality of storage capacitive elements, each of the storage capacitive elements having a dielectric on and contacting a conductive channel, the conductive channel located between
What is claimed is: 1. An integrated circuit comprising: memory, comprising flash memory, the flash memory including a plurality of storage capacitive elements, each of the storage capacitive elements having a dielectric on and contacting a conductive channel, the conductive channel located between a first region and a second region, wherein electrical conductivity of the conductive channel is modulated by a voltage, the dielectric configured to electrically couple the first region and the second region using the conductive channel, the dielectric structured as a dielectric stack including at least one TayAlzOxNw (y>0, z>0, x>0, w>0) layer such that concentration of nitrogen in the TayAlzOxNw (y>0, z>0, x>0, w>0) is graded in the dielectric, the dielectric stack including at least one insulator layer without TayAlzOxNw (y>0, z>0, x>0, w>0) such that the dielectric stack includes a layer of tantalum oxide, a layer of aluminum oxide, or both a layer of tantalum oxide and a layer of aluminum oxide, the dielectric stack interposed between at least two electrodes. 2. The integrated circuit of claim 1, wherein the memory includes a plurality of silicon-based CMOS transistors. 3. The integrated circuit of claim 1, wherein the memory includes at least one of a PMOS transistor or a NMOS transistor. 4. The integrated circuit of claim 3, wherein the at least one of a PMOS transistor or a NMOS transistor includes a TaAlON gate dielectric. 5. An integrated circuit comprising: a plurality of insulated gate field effect transistors, each of the plurality including one or more gate dielectric layers; a memory, at least a portion of the memory including a one or more capacitive storage elements, wherein the capacitive storage elements include a dielectric on and contacting a conductive channel, the conductive channel located between a first region and a second region, wherein electrical conductivity of the conductive channel is modulated by a voltage, the dielectric configured to electrically couple the first region and the second region using the conductive channel, the dielectric structured as a dielectric stack including a TayAlzOxNw (y>0, z>0, x>0, w>0) dielectric layer such that concentration of nitrogen in the TayAlzOxNw (y>0, z>0, x>0, w>0) is graded in the dielectric, the dielectric stack including at least one insulator layer without TayAlzOxNw (y>0, z>0, x>0, w>0) such that the dielectric stack includes a layer of tantalum oxide, a layer of aluminum oxide, or both a layer of tantalum oxide and a layer of aluminum oxide; and a plurality of conductive layers, wherein at least one of the plurality of conductive layers is supported by at least a portion of the TayAlzOxNw (y>0, z>0, x>0, w>0) dielectric layer. 6. The integrated circuit of claim 5, wherein at least a portion of the one or more gate dielectric layers includes TaAlON. 7. The integrated circuit of claim 5, wherein a portion of the plurality of insulated gate field effect transistors is electrically coupled to at least a portion of the one or more capacitive storage elements. 8. The integrated circuit of claim 5, wherein a portion of the plurality of insulated gate field effect transistors is configured to comprise a mixed signal circuit. 9. The integrated circuit of claim 5, wherein a portion of the plurality of insulated gate field effect transistors is configured to comprise an analog circuit. 10. The integrated circuit of claim 5, wherein the memory includes a DRAM or a flash memory. 11. An electronic device comprising: a conductive channel located between a first region and a second region, wherein the electrical conductivity of the conductive channel is modulated by a voltage; and a dielectric on and contacting the conductive channel, the dielectric including TayAlzOxNw (y>0, z>0, x>0, w>0) such that concentration of nitrogen in the TayAlzOxNw (y>0, z>0, x>0, w>0) is graded in the dielectric, the dielectric configured to electrically couple the first region and the second region using the conductive channel, wherein the dielectric is structured as a dielectric stack including at least one insulator layer without TayAlzOxNw (y>0, z>0, x>0, w>0) such that the dielectric stack includes a layer of tantalum oxide, a layer of aluminum oxide, or both a layer of tantalum oxide and a layer of aluminum oxide. 12. The electronic device of claim 11, wherein the at least one insulator layer without TayAlzOxNw (y>0, z>0, x>0, w>0) is an amorphous insulator layer. 13. The electronic device of claim 11, wherein the at least one insulator layer without TayAlzOxNw (y>0, z>0, x>0, w>0) includes a metal oxide without nitrogen. 14. The electronic device of claim 13, wherein the TayAlzOxNw (y>0, z>0, x>0, w>0) is amorphous. 15. The electronic device of claim 13, wherein the dielectric is disposed as a tunnel insulator layer in direct contact with the conductive channel. 16. A memory element comprising: two or more electrode layers; and insulator layers disposed on and arranged such that at least one of the insulator layers contacts a conductive channel, the conductive channel located between a first region and a second region, wherein electrical conductivity of the conductive channel is modulated by a voltage, the insulator layers configured to electrically couple the first region and the second region using the conductive channel, the insulator layers including a nanolaminate in which TayAlzOxNw (y>0, z>0, x>0, w>0) is disposed such that concentration of nitrogen in the TayAlzOxNw (y>0, z>0, x>0, w>0) is graded in the insulator layers, the insulator layers including at least one insulator layer without TayAlzOxNw (y>0, z>0, x>0, w>0) such that the insulator layers includes a layer of tantalum oxide, a layer of aluminum oxide, or both a layer of tantalum oxide and a layer of aluminum oxide, wherein at least a portion of the insulator layers is configured to couple electric charge between the two or more electrodes, wherein the nanolaminate includes a TaON layer. 17. The memory element of claim 16, wherein the nanolaminate includes a layer of a metal oxynitride different from TayAlzOxNw (y>0, z>0, x>0, w>0). 18. The memory element of claim 17, wherein the metal oxynitride is a non-stoichiometric metal oxynitride. 19. The memory element of claim 17, wherein the nanolaminate includes an amorphous metal oxynitride. 20. The memory element of claim 16, wherein the insulator layers includes one or more TayAlzOxNw layers, where y, z, x, w are integer values, and where y is 1 or 2, z is 1 or 2, x is 0, 1, 3 or 5, and w is 0 or 1. 21. The memory element of claim 20, wherein at least one of the one or more TayAlzOxNw layers has a stoichiometric structure. 22. The memory element of claim 16, wherein the nanolaminate includes TaAlO. 23. The memory element of claim 22, wherein the nanolaminate includes a TaAlON tunnel insulator layer. 24. The memory element of claim 16, wherein the two or more electrodes are configured to form at least a portion of a flash memory circuit. 25. The memory element of claim 16, wherein the nanolaminate includes at least one of a Ta2O5/Al2O3, a TaON/AlON, a Ta2O5/AlN, TaN/Al2O3, or a TaN/AlN structure. 26. A system comprising: a processor; a memory, wherein a portion of the memory includes: a conductive channel located between a first region and a second region, wherein the electrical conductivity of the conductive channel is modulated by a voltage; and a dielectric on and contacting the conductive channel, the dielectric structured as a dielectric stack including TayAlzOxNw (y>0, z>0, x>0, w>0) such that concentration of nitrogen in the TayAlzOxNw (y>0, z>0, x>0, w>0) is graded in the dielectric, the dielectric configured to electrically couple the first region and the second region using the conductive channel, the dielectric stack including at least one insulator layer without TayAlzOxNw (y>0, z>0, x>0, w>0) such that the dielectric stack includes a layer of tantalum oxide, a layer of aluminum oxide, or both a layer of tantalum oxide and a layer of aluminum oxide; and a data bus electrically coupled to the processor and the memory. 27. The system of claim 26, wherein the memory includes at least one of a DRAM, a SRAM or a flash memory. 28. The system of claim 26, wherein the dielectric comprises a nanolaminate structure including at least one of a Ta2O5/Al2O3, a TaON/AlON, a Ta2O5/AlN, a TaN/Al2O3, or a TaN/AlN. 29. The system of claim 26, wherein at least one of the nitrogen content and the oxygen content of the TayAlzOxNw is less than 40%. 30. The electronic device of claim 13, wherein the dielectric includes a nanolaminate in which the TayAlzOxNw (y>0, z>0, x>0, w>0) is disposed. 31. An electronic device comprising: a conductive channel located between a first region and a second region, wherein the electrical conductivity of the conductive channel is modulated by a voltage; and a dielectric on and contacting the conductive channel, the dielectric including TayAlzOxNw (y>0, z>0, x>0, w>0) such that concentration of nitrogen in the TayAlzOxNw (y>0, z>0, x>0, w>0) is graded in the dielectric, the dielectric configured to electrically couple the first region and the second region using the conductive channel, wherein the dielectric includes a nanolaminate in which the TayAlzOxNw (y>0, z>0, x>0, w>0) is disposed, wherein the nanolaminate includes a TaON layer. 32. The electronic device of claim 31, wherein the nanolaminate includes layers of tantalum oxide without aluminum and tantalum oxynitride without aluminum in an alternating arrangement with one or more layers of TayAlzOxNw (y>0, z>0, x>0, w>0). 33. The electronic device of claim 31, wherein the dielectric includes a layer of TajOk (j>0, k>0), a layer of AllOmNn (l>0, m>0, n>0), a layer of AlpOq (p>0, q>0), and a layer of TarOsNt (r>0, s>0, t>0). 34. The electronic device of claim 31, wherein the dielectric includes silicon oxide. 35. The electronic device of claim 31, wherein the dielectric contacts a metal layer. 36. The electronic device of claim 13, wherein the channel includes germanium, silicon-germanium, or gallium arsenide. 37. The electronic device of claim 13, wherein the concentration of nitrogen in the TayAlzOxNw (y>0, z>0, x>0, w>0) is graded substantially parallel to the conductive channel. 38. The electronic device of claim 13, wherein the concentration of nitrogen in the TayAlzOxNw (y>0, z>0, x>0, w>0) is graded substantially perpendicular to the conductive channel.
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