초록 ▼

Techniques for a processor temperature control interface. In one embodiment, a processor includes a bidirectional interface and output logic to assert a first signal indicating an internal high temperature on the bidirectional interface. Throttling logic throttles operations of the processor if eith

Techniques for a processor temperature control interface. In one embodiment, a processor includes a bidirectional interface and output logic to assert a first signal indicating an internal high temperature on the bidirectional interface. Throttling logic throttles operations of the processor if either the internal high temperature is indicated or if an external signal is received on the bidirectional interface.

대표청구항 ▼

What is claimed is: 1. A processor comprising: a bidirectional interface; output logic to assert a first signal indicating an internal high temperature on said bidirectional interface; throttling logic coupled to said bidirectional interface, said throttling logic to throttle operations of said pro

What is claimed is: 1. A processor comprising: a bidirectional interface; output logic to assert a first signal indicating an internal high temperature on said bidirectional interface; throttling logic coupled to said bidirectional interface, said throttling logic to throttle operations of said processor if either said internal high temperature is indicated by said first signal or if an external signal is received on said bidirectional interface, wherein said internal high temperature is indicated by a signal transmitted on the bidirectional interface to indicate whether the internal high temperature has reached an unacceptable level, and further comprising an external high temperature is indicated by a signal from a second processor indicating whether the second processor's internal high temperature has reached an unacceptable level. 2. The processor of claim 1 wherein said bidirectional interface is a single interface node. 3. The processor of claim 1 further comprising: a first path for said first signal; a second path for said external signal; selection logic to select between said first path which disregards the external signal in a unidirectional mode and said second path which considers said external signal in a bidirectional single interface mode. 4. The processor of claim 3 wherein said bidirectional interface comprises a first interface node and a second interface node, the second interface node being an input, the selection logic to further select a third path in a bidirectional dual interface mode. 5. The processor of claim 4 wherein said third path comprises: an internal signal path for said first signal having a first delay; an external signal path for said external signal having a second delay, said first delay to match the second delay plus an external delay. 6. The processor of claim 1 wherein said bidirectional interface further comprises: a single bidirectional interface node when a bidirectional mode is enabled. 7. The processor of claim 6 further comprising: a first delay in a first path of said first signal; a second delay in a second path of said external signal, wherein said first delay in said first path matches said second delay in said second path plus an external delay. 8. A system comprising: a first processor comprising: a bidirectional interface; throttling logic to throttle said first processor in response to the internal signal or the external signal, wherein said internal signal indicates whether an internal temperature has reached an unacceptable level, and wherein the internal signal is transmitted on the bidirectional interface; system logic to assert said external signal; and a second processor comprising: a second processor first interface node to output a second processor internal signal indicating a second processor high temperature; a second processor second interface node to receive a second external signal; second processor throttling logic to throttle said second processor in response to the second processor internal signal or the second external signal; wherein said system logic is to assert said external signal to said first processor in response said second processor outputting said second processor internal signal indicating whether said second processor high temperature has reached an unacceptable level. 9. The system of claim 8 wherein said first processor further comprises: a first delay in a first path of said internal signal to said throttling logic; a second delay in a second path of said external signal to said throttling logic, said first delay to match said second delay plus a system logic delay. 10. The system of claim 9 wherein said first processor and said second processor are to commence throttling in synchroniiation in response to said second processor internal signal. 11. The system of claim 10 wherein said first processor and said second processor are to commence throttling in a same single clock cycle. 12. A method comprising: driving a first signal to a first processor indicating an internally measured high temperature of a second processor on a bidirectional interface; throttling operations by the first processor if either said first signal is driven or if an external signal is received on said bidirectional interface, wherein the internal high temperature of the second processor is indicated by a signal to indicate whether the internal high temperature of the second processor has reached an unacceptable level. 13. The method of claim 12 wherein driving comprises: testing if a selected thermal metric is reached; driving the first signal if said selected thermal metric is reached. 14. The method of claim 12 wherein said interface node is a single bidirectional interface node. 15. The method of claim 12 further comprising delaying the first signal and the external signal through different delay paths. 16. The method of claim 12 further comprising selecting either a first mode using a single bidirectional interface node as the interface node or a second mode using two interface nodes. 17. The method of claim 16 further comprising: delaying, in the second mode, the first signal to cause throttling at the same time as another processor.