초록 ▼

Embodiments of the present invention provide Forward Error Correcting Code encoders and decoder structures that use DRAM in their memory designs. DRAM is a very attractive memory options in many electronic systems due to the high memory density provided by DRAM. However, the DRAM is typically not in

Embodiments of the present invention provide Forward Error Correcting Code encoders and decoder structures that use DRAM in their memory designs. DRAM is a very attractive memory options in many electronic systems due to the high memory density provided by DRAM. However, the DRAM is typically not included in ASIC or FPGA implementations of encoders and decoders due to complex refresh requirements of DRAM that are required to maintain data stored in DRAM and may interfere with user access to the memory space during refresh cycles. Embodiments of the present invention provide FECC encoder and decoder structures that are implemented using DRAM that do not require complex refresh operations to be performed on the DRAM to ensure data integrity. Accordingly, embodiments of the present invention maximize memory density without the added complexity of introduced by the refresh requirements of DRAM.

대표청구항 ▼

What is claimed is: 1. A method for utilizing memory to perform error correction code (ECC) operations, the method comprising: obtaining data to be operated upon according to an ECC operation; temporarily storing the data to be operated upon in volatile memory configured for maintaining stored data

What is claimed is: 1. A method for utilizing memory to perform error correction code (ECC) operations, the method comprising: obtaining data to be operated upon according to an ECC operation; temporarily storing the data to be operated upon in volatile memory configured for maintaining stored data values for a time duration with an expiration; reading the data to be operated upon from the volatile memory prior to the expiration of the time duration, wherein the data to be operated upon is read once from the volatile memory without performing any refresh operation on the data; and performing the ECC operation on the retrieved data. 2. The method of claim 1 wherein the volatile memory comprises Dynamic Random Access Memory (DRAM). 3. The method of claim 2 wherein the DRAM is used to implement an input buffer. 4. The method of claim 2 wherein the DRAM is used to implement an output buffer. 5. The method of claim 2 wherein the DRAM is used to implement at least one of an interleaver operation and a de-interleaver operation. 6. The method of claim 1 wherein the ECC operation is an ECC encoding operation. 7. The method of claim 1 wherein the ECC operation is an ECC decoding operation. 8. The method of claim 1 wherein the ECC operation is part of an iterative ECC process. 9. The method of claim 1 wherein the data to be operated upon is read multiple times from the volatile memory, each read being associated with a refresh operation on the data, the refresh operation extending the limited duration by which the volatile memory maintains stored data. 10. An apparatus configured to utilize memory to perform error correction code (ECC) operations, the apparatus comprising: volatile memory configured for maintaining stored data values for a time duration with an expiration; and an ECC module comprising: logic to obtain data to be operated upon according to an ECC operation; logic to send the data to be operated upon to the volatile memory for temporary storage; logic to read the data to be operated upon from the volatile memory prior to the expiration of a the time duration, wherein the ECC module is configured to read the data to be operated upon from the volatile memory without performing any refresh operation on the data; and logic to perform the ECC operation on the retrieved data. 11. The apparatus of claim 10 wherein the volatile memory comprises Dynamic Random Access Memory (DRAM). 12. The apparatus of claim 11 wherein the DRAM is used to implement an input buffer. 13. The apparatus of claim 11 wherein the DRAM is used to implement an output buffer. 14. The apparatus of claim 11 wherein the DRAM is used to implement at least one of an interleaver operation and a de-interleaver operation. 15. The apparatus of claim 10 wherein the ECC operation is an ECC encoding operation. 16. The apparatus of claim 10 wherein the ECC operation is an ECC decoding operation. 17. The apparatus of claim 10 wherein the ECC operation is part of an iterative ECC process. 18. The apparatus of claim 10 wherein the ECC module is configured to read the data to be operated upon multiple times from the volatile memory, each read being associated with a refresh operation on the data, the refresh operation extending the limited duration by which the volatile memory maintains stored data.