[특허]On chip temperature measuring and monitoring method

On chip temperature measuring and monitoring method 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	G01K-007/00
출원번호	UP-0061692 (2008-04-03)
등록번호	US-7762721 (2010-08-13)
발명자 / 주소	Franch, Robert L. Jenkins, Keith A.
출원인 / 주소	International Business Machines Corporation
대리인 / 주소	Law Office of Charles W. Peterson, Jr.
인용정보	피인용 횟수 : 0 인용 특허 : 58

초록 ▼

A device temperature measurement circuit, an integrated circuit (IC) including a device temperature measurement circuit, a method of characterizing device temperature and a method of monitoring temperature. The circuit includes a constant current source and a clamping device. The clamping device selectively shunts current from the constant current source or allows the current to flow through a PN junction, which may be the body to source/drain junction of a field effect transistor (FET). Voltage measurements are taken directly from the PN junction. Junction temperature is determined from measured junction voltage.

대표청구항 ▼

What is claimed is: 1. A method of modeling a field effect transistor (FET) in a circuit on an integrated circuit (IC) chip, said FET being modeled for varying temperature, said method comprising: determining a voltage to temperature relationship for a PN junction at a known current, said PN junction being a body to source/drain junction of a FET included in an inverter in a ring oscillator including said inverter and; operating said FET normally; and stopping oscillation of said ring oscillator and measuring voltage across said PN junction, measured said voltage indicating the instantaneous temperature of said PN junction, a device temperature model being derived from indicated said instantaneous temperature. 2. A method of modeling said FET as in claim 1, wherein determining said voltage to temperature relationship for the PN junction comprises: ramping temperature on said PN junction; providing said known current to said PN junction from an on-chip current source; and measuring voltage across said PN junction until a maximum selected temperature is reached. 3. A method of modeling said FET as in claim 2, wherein providing said known current, said voltage is periodically measured. 4. A method of modeling said FET as in claim 1, wherein operating the FET normally comprises reducing current provided from an on-chip current source to said PN junction. 5. A method of modeling said FET as in claim 4, wherein said on-chip current source is a constant current source and reducing current comprises shunting said constant current source, whereby voltage across said PN junction is below a turn on point for said PN junction. 6. A method of modeling said FET as in claim 1, wherein measuring comprises halting operation of said FET. 7. A method of modeling said FET as in claim 1, wherein stopping said ring oscillator further comprises turning off a shunt shunting current from an on chip current source, said current flowing through said PN junction. 8. A method of modeling said FET as in claim 7, wherein stopping oscillation and measuring further comprises periodically measuring said voltage across said PN junction.

이 특허에 인용된 특허 (58)

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IPC	Description
A	생활필수품
A62	인명구조; 소방(사다리 E06C)
A62B	인명구조용의 기구, 장치 또는 방법(특히 의료용에 사용되는 밸브 A61M 39/00; 특히 물에서 쓰이는 인명구조 장치 또는 방법 B63C 9/00; 잠수장비 B63C 11/00; 특히 항공기에 쓰는 것, 예. 낙하산, 투출좌석 B64D; 특히 광산에서 쓰이는 구조장치 E21F 11/00)
A62B-1/08	.. 윈치 또는 풀리에 제동기구가 있는 것

내보내기 구분	파일저장 인쇄 메일전송
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저장형식	Text(ASCII format) Excel format PIAS분석(.xls)
메일정보	받는사람 (필수) @ 보내는사람 (선택) @ 제목 내용 KISTI 검색결과 이메일 서비스
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On chip temperature measuring and monitoring method 원문보기

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On chip temperature measuring and monitoring method 원문보기

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