Use of hybrid interconnect/logic circuits for multiplication
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
G06F-007/38
G06F-007/52
출원번호
UP-0269518
(2005-11-07)
등록번호
US-7765249
(2010-08-13)
발명자
/ 주소
Pugh, Daniel J.
Schmit, Herman
Redgrave, Jason
Caldwell, Andrew
출원인 / 주소
Tabula, Inc.
대리인 / 주소
Adeli & Tollen LLP
인용정보
피인용 횟수 :
2인용 특허 :
153
초록▼
Some embodiments of the invention provide a configurable integrated circuit (“IC”). The configurable IC includes a set of configurable logic circuits for configurably performing a set of functions on a set of inputs. The IC also includes several input select interconnect circuits for s
Some embodiments of the invention provide a configurable integrated circuit (“IC”). The configurable IC includes a set of configurable logic circuits for configurably performing a set of functions on a set of inputs. The IC also includes several input select interconnect circuits for selecting the input set supplied to each configurable logic circuit. Each input select interconnect circuit is associated with a particular configurable logic circuit. When a configurable logic circuit is used to perform a multiplication operation, at least one of its associated input select interconnect circuits performs a logic operation that implements part of the multiplication operation.
대표청구항▼
We claim: 1. An integrated circuit (“IC”) comprising: a set of configurable logic circuits, each configurable logic circuit for configurably performing a set of functions on a set of inputs; and a plurality of input select interconnect circuits for selecting the set of inputs supplied
We claim: 1. An integrated circuit (“IC”) comprising: a set of configurable logic circuits, each configurable logic circuit for configurably performing a set of functions on a set of inputs; and a plurality of input select interconnect circuits for selecting the set of inputs supplied to each configurable logic circuit, wherein each input select interconnect circuit is associated with a particular configurable logic circuit, wherein for at least one particular configurable logic circuit that is used to perform a multiplication operation, at least one associated input select interconnect circuit of the particular configurable logic circuit performs a logic operation that implements part of the multiplication operation, wherein the logic operation performed by the input select interconnect circuit when it is implementing part of the multiplication operation is an AND operation. 2. The IC of claim 1 further comprising a plurality of adders and multipliers arranged in an asymmetrical tree. 3. The IC of claim 2, wherein the asymmetrical tree has multiple levels wherein no two adders appear in a same level in the asymmetrical tree. 4. The IC of claim 1 further comprising a plurality of adders and multipliers arranged in a binary tree. 5. The IC of claim 4, wherein the binary tree has multiple levels, wherein each adder in a first level receives inputs from two multipliers and each adder in subsequent levels receives inputs from up to two adders in a previous level. 6. The IC of claim 1, wherein the input select interconnect circuit that performs the logic operation is a hybrid interconnect/logic circuit. 7. The IC of claim 6, wherein the hybrid interconnect/logic circuit has a set of select lines, wherein the hybrid interconnect/logic circuit operates as an interconnect circuit when it receives only configuration data at the hybrid interconnect/logic circuit's select lines and operates as a logic circuit when it receives at least one user design signal at one of the hybrid interconnect/logic circuit's select lines. 8. An integrated circuit (“IC”) comprising: a set of configurable logic circuits, each configurable logic circuit for configurably performing a set of functions on a set of inputs; and a plurality of input select interconnect circuits for selecting the set of inputs supplied to each configurable logic circuit, wherein each input select interconnect circuit is associated with a particular configurable logic circuit, wherein for at least one particular configurable logic circuit that is used to perform a multiplication operation, at least one associated input select interconnect circuit of the particular configurable logic circuit performs a logic operation that implements part of the multiplication operation, wherein the multiplication operation is broken into a set of AND operations and a set of add operations, wherein the set of configurable logic circuits are utilized to perform the add operations and a set of input select interconnect circuits are utilized to perform the AND operations to generate a result of the multiplication operation. 9. An integrated circuit (“IC”) comprising: a set of configurable logic circuits, each configurable logic circuit for configurably performing a set of functions on a set of inputs; and a plurality of input select interconnect circuits for selecting the set of inputs supplied to each configurable logic circuit, wherein each input select interconnect circuit is associated with a particular configurable logic circuit, wherein for at least one particular configurable logic circuit that is used to perform a multiplication operation, at least one associated input select interconnect circuit of the particular configurable logic circuit performs a logic operation that implements part of the multiplication operation, wherein the multiplication operation is a multiplication between a first operand and a second operand, wherein the implements a first-type multiplier to perform the multiplication operation, wherein the first-type multiplier comprises a set of adders comprising a set of logic circuits and their associated input select interconnect circuits, wherein at least one input-select interconnect circuit performs an AND operation between a bit of the first operand and a bit of the second operand. 10. The IC of claim 9, wherein one of said configurable logic circuits is a first configurable logic circuit, wherein the first configurable logic circuit and the associated input select interconnect circuit of the first configurable logic circuit generate a least significant bit of the multiplication operation, wherein either the associated input select interconnect circuit of the first configurable logic circuit or the first configurable logic circuit implements an AND operation. 11. The IC of claim 9, wherein each adder has a carry-in and a carry-out, wherein the adders are connected together in a chain, wherein for several of the adders in the chain the carry-out of each adder is connected to the carry-in of a next adder in the chain. 12. The IC of claim 11, wherein the carry-in of a first adder in the chain has a value of zero. 13. The IC of claim 11, wherein the carry-out of a last adder in the chain is not connected to carry-in of any adders and is used as a most significant bit of the multiplication operation. 14. The IC of claim 9, further implementing a second-type multiplier, wherein the second-type multiplier comprises: a) a plurality of said first-type multipliers; and b) a plurality of sets of multi-bit adders, wherein all multi-bit adders in a set have a same number of bits, wherein each multi-bit adder in a first set shiftably adds a result of one first-type multiplier to a result of another first-type multiplier, wherein each multi-bit adder in sets other than the first set shiftably adds a result of a multi-bit adder of a previous set to a result of another multi-bit adder in said previous set. 15. The IC of claim 9, further implementing a second-type multiplier, wherein the second-type multiplier comprises: a) a plurality of said first-type multipliers; and b) a plurality of multi-bit adders, wherein all multi-bit adders have a same number of bits, wherein a first multi-bit adder shiftably adds a result of one first-type multiplier to a result of a second first-type multiplier, wherein all other multi-bit adders shiftably add a result of one first-type multiplier to a result of a previous multi-bit adder. 16. An electronic system comprising: an integrated circuit (“IC”) comprising: i) a set of configurable logic circuits, each configurable logic circuit for configurably performing a set of functions on a set of inputs; and ii) a plurality of input select interconnect circuits for selecting the set of inputs supplied to each configurable logic circuit, iii) wherein each input select interconnect circuit is associated with a particular configurable logic circuit, iv) wherein for at least one configurable logic circuit that is used to perform a multiplication operation, at least one associated input select interconnect circuit of the configurable logic circuit performs a logic operation that implements part of the multiplication operation, wherein the multiplication operation is broken into a set of AND operations and a set of add operations, wherein the set of configurable logic circuits are utilized to perform the add operations and a set of input select interconnect circuits are utilized to perform the AND operations to generate a result of the multiplication operation. 17. The electronic system of claim 16, wherein the input select interconnect circuit that performs the logic operation is a hybrid interconnect/logic circuit. 18. The electronic system of claim 17, wherein the hybrid interconnect/logic circuit has a set of select lines, wherein the hybrid interconnect/logic circuit operates as an interconnect circuit when it receives only configuration data at the hybrid interconnect/logic circuit's select lines and operates as a logic circuit when it receives at least one user design signal at one of the hybrid interconnect/logic circuit's select lines. 19. The electronic system of claim 16 further comprising a non-volatile memory for storing configuration data and for supplying configuration data to the IC when the IC powers up. 20. The electronic system of claim 19, wherein the non-volatile memory and the IC are on different IC dies. 21. The electronic system of claim 19, wherein the non-volatile memory and the IC are on a same IC die.
연구과제 타임라인
LOADING...
LOADING...
LOADING...
LOADING...
LOADING...
이 특허에 인용된 특허 (153)
Ting, Benjamin S., Architecture and interconnect scheme for programmable logic circuits.
Schmit, Herman; Teig, Steven; Hutchings, Brad; Huang, Randy Renfu; Redgrave, Jason, Configurable IC with configurable routing resources that have asymmetric input and/or outputs.
Schmit, Herman; Teig, Steven; Hutchings, Brad; Huang, Randy Renfu; Redgrave, Jason, Configurable IC with configuration logic resources that have asymmetric inputs and/or outputs.
Andy L. Lee ; Christopher F. Lane ; Srinivas T. Reddy ; Brian D. Johnson ; Ketan H. Zaveri ; Mario Guzman ; Quyen Doan, Configurable memory structures in a programmable logic device.
Trimberger Stephen M. (San Jose CA) Carberry Richard A. (Los Gatos CA) Johnson Robert A. (San Jose CA) Wong Jennifer (Fremont CA), Configuration modes for a time multiplexed programmable logic device.
Wakayama Shigetoshi,JPX ; Gotoh Kohtaroh,JPX ; Saito Miyoshi,JPX ; Ogawa Junji,JPX, Destructive read type memory circuit, restoring circuit for the same and sense amplifier.
Nguyen Bai ; Agrawal Om P. ; Sharpe-Geisler Bradley A. ; Wong Jack T. ; Chang Herman M., Efficient interconnect network for use in FPGA device having variable grain architecture.
Agrawal, Om P.; Fontana, Fabiano; Bosco, Gilles M., Enhanced CPLD macrocell module having selectable bypass of steering-based resource allocation and methods of use.
Tavana Danesh (Mountain View CA) Yee Wilson K. (Tracy CA) Holen Victor A. (Saratoga CA), FPGA architecture with repeatable tiles including routing matrices and logic matrices.
Iadanza Joseph Andrew ; Kilmoyer Ralph David ; Laramie Michael Joseph ; Seidel Victor Paul ; Zittritsch Terrance John, Field programmable memory array.
Bennett David Wayne (Louisville CO) Dellinger Eric Ford (Boulder CO) Manaker ; Jr. Walter A. (Boulder CO) Stern Carl M. (Boulder CO) Troxel William R. (Longmont CO) Young Jay Thomas (Louisville CO), Frequency driven layout and method for field programmable gate arrays.
Rostoker Michael D. ; Koford James S. ; Scepanovic Ranko ; Jones Edwin R. ; Padmanahben Gobi R. ; Kapoor Ashok K. ; Kudryavtsev Valeriy B.,RUX ; Andreev Alexander E.,RUX ; Aleshin Stanislav V.,RUX ; , Hexagonal field programmable gate array architecture.
Pugh,Daniel J.; Caldwell,Andrew, Hybrid interconnect/logic circuits enabling efficient replication of a function in several sub-cycles to save logic and routing resources.
Vorbach,Martin; M체nch,Robert, Internal bus system for DFPS and units with two-or multi-dimensional programmable cell architectures, for managing large volumes of data with a high interconnection complexity.
Goetting F. Erich (Cupertino CA) Trimberger Stephen M. (San Jose CA), Logic cell for field programmable gate array having optional internal feedback and optional cascade.
Norman Kevin A. ; Patel Rakesh H. ; Sample Stephen P. ; Butts Michael R., Look-up table based logic element with complete permutability of the inputs to the secondary signals.
Chiang David (Saratoga CA) Lee Napoleon W. (Fremont CA) Ho Thomas Y. (Milpitas CA) Harrison David A. (Cupertino CA) Kucharewski ; Jr. Nicholas (Pleasanton CA) Seltzer Jeffrey H. (San Jose CA), Macrocell with product-term cascade and improved flip flop utilization.
Clinton Kim P. N. ; Iadanza Joseph Andrew ; Keyser ; III Frank Ray ; Seidel Victor Paul ; Zittritsch Terrance John, Memory cells for field programmable memory array.
Poplingher Mircea ; Chen Wenliang ; Suryanarayanan Ganesh ; Chen Wayne W. ; Lo Roger Y., Memory device for a microprocessor register file having a power management scheme and method for copying information between memory sub-cells in a single clock cycle.
Larsen Wendell Ray (Essex Junction VT) Keyser Frank Ray (Colchester VT) Worth Brian A. (Milton VT), Memory mapping method and apparatus to fold sparsely populated structures into densely populated memory columns or rows.
Fuller Christine Marie ; Hartman Steven Paul ; Millham Eric Ernest, Method and system for optimizing a critical path in a field programmable gate array configuration.
Craft David John ; Gould Scott Whitney ; Keyser ; III Frank Ray ; Worth Brian, Method and system for programming a gate array using a compressed configuration bit stream.
Bailis, Robert Thomas; Kuhlmann, Charles Edward; Lingafelt, Charles Steven; Rincon, Ann Marie, Method and system for use of a field programmable function within a chip to enable configurable I/O signal timing characteristics.
Bailis, Robert Thomas; Kuhlmann, Charles Edward; Lingafelt, Charles Steven; Rincon, Ann Marie, Method and system for use of a field programmable function within a standard cell chip for repair of logic circuits.
Bailis, Robert Thomas; Kuhlmann, Charles Edward; Lingafelt, Charles Steven; Rincon, Ann Marie, Method and system for use of a field programmable interconnect within an ASIC for configuring the ASIC.
Bailis, Robert Thomas; Kuhlmann, Charles Edward; Lingafelt, Charles Steven; Rincon, Ann Marie, Method and system for use of an embedded field programmable gate array interconnect for flexible I/O connectivity.
Gould Scott Whitney ; Iadanza Joseph Andrew ; Keyser ; III Frank Ray ; Zittritsch Terrance John, Method of operating a field programmable memory array with a field programmable gate array.
Trimberger Stephen M. (San Jose CA) Carberry Richard A. (Los Gatos CA) Johnson Robert A. (San Jose CA) Wong Jennifer (Fremont CA), Method of time multiplexing a programmable logic device.
Leventis,Paul; Pedersen,Bruce; Lane,Chris; Reddy,Srinivas; Lewis,David, Multiplexing device including a hardwired multiplexer in a programmable logic device.
Gould Scott Whitney ; Iadanza Joseph Andrew ; Keyser ; III Frank Ray ; Zittritsch Terrance John, Programmable address decoder for field programmable memory array.
Clinton Kim P. N. (Essex Junction VT) Gould Scott W. (South Burlington VT) Hartman Steven P. (Jericho VT) Iadanza Joseph A. (Hinesburg VT) Keyser ; III Frank R. (Colchester VT) Millham Eric E. (St. G, Programmable array interconnect network.
El Gamal Abbas A. (Palo Alto CA) El-Ayat Khaled A. (Cupertino CA) Greene Jonathan W. (Palo Alto CA) Guo Ta-Pen R. (Cupertino CA) Reyneri Justin M. (Los Altos CA), Programmable interconnect architecture.
Motomura Masato,JPX, Programmable logic IC having memories for previously storing a plurality of configuration data and a method of reconfigurating same.
New Bernard J. ; Johnson Robert Anders ; Wittig Ralph ; Mohan Sundararajarao, Rapidly reconfigurable FPGA having a multiple region architecture with reconfiguration caches useable as data RAM.
Blodget, Brandon J.; McMillan, Scott P.; James-Roxby, Philip B.; Sundararajan, Prasanna; Keller, Eric R.; Curd, Derek R.; Kalra, Punit S.; LeBlanc, Richard J.; Eck, Vincent P., Reconfiguration of a programmable logic device using internal control.
Om P. Agrawal ; Claudia A. Stanley ; Xiaojie (Warren) He ; Larry R. Metzger ; Robert A. Simon ; Kerry A. Ilgenstein, Scalable architecture for high density CPLD's having two-level hierarchy of routing resources.
Clinton Kim P. N. ; Gould Scott Whitney ; Iadanza Joseph Andrew ; Keyser ; III Frank Ray ; Kilmoyer Ralph David ; Laramie Michael Joseph ; Seidel Victor Paul ; Zittritsch Terrance John, Selective connectivity between memory sub-arrays and a hierarchical bit line structure in a memory array.
Agrawal Om P. ; Chang Herman M. ; Sharpe-Geisler Bradley A. ; Tran Giap H., Symmetrical, extended and fast direct connections between variable grain blocks in FPGA integrated circuits.
Iadanza Joseph Andrew ; Keyser ; III Frank Ray ; Kilmoyer Ralph David ; Laramie Michael Joseph, System for implementing write, initialization, and reset in a memory array using a single cell write port.
Balasubramanian,Rabindranath; Zhu,Limin; Speers,Theodore; Bakker,Gregory, System-on-a-chip integrated circuit including dual-function analog and digital inputs.
Trimberger Stephen M. (San Jose CA) Carberry Richard A. (Los Gatos CA) Johnson Robert Anders (San Jose CA) Wong Jennifer (Fremont CA), Time multiplexed programmable logic device.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.