Nanowire electronic devices and method for producing the same
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H01L-021/3205
출원번호
UP-0837364
(2007-08-10)
등록번호
US-7767564
(2010-08-24)
발명자
/ 주소
Dutta, Biprodas
출원인 / 주소
ZT3 Technologies, Inc.
대리인 / 주소
Foley & Lardner LLP
인용정보
피인용 횟수 :
7인용 특허 :
46
초록▼
The present invention is directed to an electrical device that comprises a first and a second fiber having a core of thermoelectric material embedded in an electrically insulating material, and a conductor. The first fiber is doped with a first type of impurity, while the second fiber is doped with
The present invention is directed to an electrical device that comprises a first and a second fiber having a core of thermoelectric material embedded in an electrically insulating material, and a conductor. The first fiber is doped with a first type of impurity, while the second fiber is doped with a second type of impurity. A conductor is coupled to the first fiber to induce current flow between the first and second fibers.
대표청구항▼
The invention claimed is: 1. A method of making a field effect transistor, comprising: introducing a sealed glass tube containing a semiconductor material into a heating device; increasing a temperature within the heating device above the semiconductor material melting temperature such that the mat
The invention claimed is: 1. A method of making a field effect transistor, comprising: introducing a sealed glass tube containing a semiconductor material into a heating device; increasing a temperature within the heating device above the semiconductor material melting temperature such that the material melts and the glass tube is heated enough for it to be drawn; drawing the tube to form a glass clad semiconductor fiber of a first conductivity type; forming a gate electrode adjacent to the glass clad fiber such that the glass cladding of the fiber forms a gate insulating layer of the transistor and the semiconductor material of the first conductivity type forms a channel region of the transistor; and doping opposing ends of the fiber to form source and drain regions of a second conductivity type in opposing ends of the fiber. 2. The method of claim 1, further comprising: sealing off one end of the glass tube such that the tube has an open end and a closed end; introducing the semiconductor material inside the glass tube in granular form; evacuating the glass tube; and heating a portion of the glass tube such that the glass partially melts forming the sealed glass tube. 3. The method of claim 1, wherein an inversion region is created in the channel region when the gate electrode is biased. 4. The method of claim 1, wherein the glass comprises pyrex glass, vycor glass, borosilcate glass, aluminosilicate glass, quartz glass, lead telluride-silicate glass, silicon oxide glass, lead oxide glass, tellurium dioxide glass, or combinations thereof. 5. The method of claim 1, wherein the step of forming a gate electrode comprises providing a hollow cylinder gate electrode and inserting the hollow cylinder gate electrode over the glass clad semiconductor fiber. 6. The method of claim 1, wherein the step of forming a gate electrode comprises depositing the gate electrode on or around the glass clad semiconductor fiber. 7. The method of claim 1, wherein the step of forming a gate electrode comprises drawing the gate electrode together with the glass clad semiconductor fiber. 8. The method of claim 1, further comprising exposing the source region and the drain region such that they are not covered by the glass gate insulating layer and forming a first conductor coupled to the source region and a second conductor coupled to the drain region. 9. A method of making a field effect transistor, comprising: providing a plurality of bunched glass clad continuous semiconductor fibers of a first conductivity type; drawing the bunched glass clad fibers one or more times to produce a multi-core cable having a plurality of continuous semiconductor fibers that are insulated from each other by glass cladding; forming a gate electrode adjacent to the cable such that the glass cladding of the fibers forms a gate insulating layer of the transistor and the semiconductor material of the first conductivity type of the fibers forms a channel region of the transistor; and doping opposing ends of the fibers to form source and drain regions of a second conductivity type in opposing ends of the fibers in the cable. 10. The method of claim 9, further comprising: sealing off one end of the glass tube such that the tube has an open end and a closed end; introducing the semiconductor material inside the glass tube in granular form; evacuating the glass tube; heating a portion of the glass tube such that the glass partially melts forming a sealed glass tube; introducing the sealed glass tube containing the semiconductor material into a heating device; increasing the temperature within the heating device above the semiconductor material melting temperature such that the material melts and the glass tube is heated enough for it to be drawn; and drawing a glass-clad fiber comprising one of the plurality of glass-clad continuous semiconductor fibers. 11. The method of claim 9, wherein an inversion region is created in the channel region when the gate electrode is biased and wherein the glass comprises pyrex glass, vycor glass, borosilcate glass, aluminosilicate glass, quartz glass, lead telluride-silicate glass, silicon oxide glass, lead oxide glass, tellurium dioxide glass, or combinations thereof. 12. The method of claim 9, wherein the step of forming a gate electrode comprises providing a hollow cylinder gate electrode and inserting the hollow cylinder gate electrode over the cable. 13. The method of claim 9, wherein the step of forming a gate electrode comprises depositing the gate electrode on or around the cable. 14. The method of claim 9, wherein the step of forming a gate electrode comprises drawing the gate electrode together with the bunched glass clad semiconductor fibers. 15. The method of claim 9, further comprising exposing the source region and the drain region such that they are not covered by the glass gate insulating layer and forming a first conductor coupled to the source region and a second conductor coupled to the drain region.
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