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A radiation-tolerant flash-based FPGA switching element includes a plurality of memory cells each having a memory transistor and a switch transistor sharing a floating gate. Four such memory cells are combined such that two sets of two switch transistors are wired in series and the two sets of serie

A radiation-tolerant flash-based FPGA switching element includes a plurality of memory cells each having a memory transistor and a switch transistor sharing a floating gate. Four such memory cells are combined such that two sets of two switch transistors are wired in series and the two sets of series-wired switch transistors are also wired in parallel. The four memory transistors associated with the series-parallel combination of switch transistors are all programmed to the same on or off state. The series combination prevents an “on” radiation-hit fault to one of the floating gates from creating a false connection and the parallel combination prevents an “off” radiation-hit fault to one of the floating gates from creating a false open circuit.

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What is claimed is: 1. A method for operating a radiation-tolerant FPGA switching element, comprising the steps of: providing a programmable connection between two connection nodes with a plurality of parallel paths, a first parallel path comprising a first switch transistor and a second switch tra

What is claimed is: 1. A method for operating a radiation-tolerant FPGA switching element, comprising the steps of: providing a programmable connection between two connection nodes with a plurality of parallel paths, a first parallel path comprising a first switch transistor and a second switch transistor coupled in series between the two connection nodes, a second parallel path comprising a third switch transistor and a fourth switch transistor coupled in series between the two connection nodes, each of the first through fourth switch transistors including a floating gate; providing a first memory element for the first switch transistor having a floating gate coupled to the first switch transistor; providing a second memory element for the second switch transistor having a floating gate coupled to the second switch transistor; providing a third memory element for the third switch transistor having a floating gate coupled to the third switch transistor; providing a fourth memory element for the fourth switch transistor having a floating gate coupled to the fourth switch transistor; and programming the first through fourth memory elements to place all of the switch transistors in the same state. 2. The method of claim 1, wherein programming the first through fourth memory elements places the first through fourth switch transistors in the on state. 3. The method of claim 1, wherein programming the first through fourth memory elements places the first through fourth switch transistors in the off state. 4. The method of claim 1, further comprising bridging together intermediate nodes of the plurality of parallel paths. 5. The method of claim 1, further comprising placing the first through fourth memory elements in the switching element into an array of substantially similar memory elements, wherein each of the first through fourth memory elements in the switching element is assigned to an array location more than the double strike distance away from the location of every other memory element in the switching element. 6. The method of claim 1, further comprising placing the first through fourth memory elements in the switching element into an array of substantially similar memory elements, wherein each of the first through fourth memory elements in the switching element is assigned to an array location that is not adjacent to the location of every other memory element in the switching element. 7. A method of programming radiation-tolerant FPGA switching elements, each element having (i) a plurality of parallel paths between two connection nodes, each parallel path comprising first and second switch transistors coupled in series, and (ii) an independent memory element controlling each switch transistor in each parallel path, the method comprising: determining the desired connectivity between the connection nodes for each switching element; and programming the memory elements in each switching element to place all the switch transistors in the correct state for the desired connectivity; wherein the correct state for the first through fourth switch transistors in each switching element is on when a connection is desired; and the correct state for the first through fourth switch transistors in each switching element is off when a connection is not desired. 8. A radiation-tolerant FPGA switching element, comprising: a first circuit node; a second circuit node that can be programmably connected to the first circuit node; a first switch transistor and a second switch transistor coupled in series between the first and second circuit nodes; a third switch transistor and a fourth switch transistor coupled in series between the first and second circuit nodes; a first memory element coupled to a control element of the first switch transistor; a second memory element coupled to a control element of the second switch transistor; a third memory element coupled to a control element of the third switch transistor; and a fourth memory element coupled to a control element of the fourth switch transistor, and wherein the first through fourth memory elements are all programmed to be in the same one of an on and an off state. 9. The radiation-tolerant FPGA switching element of claim 8, wherein: each of the switch transistors is a floating gate transistor; each of the memory elements is a floating gate transistor; the floating gate of the first memory element is coupled to the floating gate of the first switch transistor; the floating gate of the second memory element is coupled to the floating gate of the second switch transistor; the floating gate of the third memory element is coupled to the floating gate of the third switch transistor; and the floating gate of the fourth memory element is coupled to the floating gate of the fourth switch transistor. 10. The radiation-tolerant FPGA switching element of claim 8, wherein: each of the memory elements is a static random access memory cell having an output node; each of the switch transistors is a standard transistor having a gate; the output node of the first memory element is coupled to the gate of the first switch transistor; the output node of the second memory element is coupled to the gate of the second switch transistor; the output node of the third memory element is coupled to the gate of the third switch transistor; and the output node of the fourth memory element is coupled to the gate of the fourth switch transistor. 11. The radiation-tolerant FPGA switching element of claim 8, wherein: each of the memory elements further comprises: an output node, a power node, a ground node, a flash transistor coupled between the power node and the output node, and a flash transistor coupled between the output node and the ground node; each of the switch transistors is a standard transistor having a gate; the output node of the first memory element is coupled to the gate of the first switch transistor; the output node of the second memory element is coupled to the gate of the second switch transistor; the output node of the third memory element is coupled to the gate of the third switch transistor; and the output node of the fourth memory element is coupled to the gate of the fourth switch transistor. 12. The radiation-tolerant FPGA switching element of claim 8, wherein: each of the memory elements further comprises: an output node, a power node, a ground node, a standard load transistor coupled between the power node and the output node, and a flash transistor coupled between the output node and the ground node; each of the switch transistors is a standard transistor having a gate; the output node of the first memory element is coupled to the gate of the first switch transistor; the output node of the second memory element is coupled to the gate of the second switch transistor; the output node of the third memory element is coupled to the gate of the third switch transistor; and the output node of the fourth memory element is coupled to the gate of the fourth switch transistor. 13. The radiation-tolerant FPGA switching element of claim 8, wherein: each of the memory elements further comprises: an output node, a power node, a ground node, a load resistor coupled between the power node and the output node, and a flash transistor coupled between the output node and the ground node; each of the switch transistors is a standard transistor having a gate; the output node of the first memory element is coupled to the gate of the first switch transistor; the output node of the second memory element is coupled to the gate of the second switch transistor; the output node of the third memory element is coupled to the gate of the third switch transistor; and the output node of the fourth memory element is coupled to the gate of the fourth switch transistor. 14. The radiation-tolerant FPGA switching element of claim 8, wherein the first, second, third and fourth memory elements are SRAM cells. 15. The radiation-tolerant FPGA switching element of claim 8, wherein the first, second, third and fourth memory elements are SRAM cells comprising: first and second inverters each with an input and an output; and a first pass transistor with a source, wherein: the output of the first inverter is coupled to the input of the second inverter and the source of the first pass transistor, and the output of the second inverter is coupled to the input of the first inverter. 16. The radiation-tolerant FPGA switching element of claim 15, wherein the first, second, third and fourth memory elements are SRAM cells further comprising: a second pass transistor with a source, wherein: the source of the second pass transistor is coupled to the output of the second inverter and the input of the first inverter. 17. The radiation-tolerant FPGA switching element of claim 8, wherein: each of the first, second, third, and fourth memory elements is part of an array of memory elements; and none of the first, second, third, and fourth memory elements is placed in the array of memory elements in a location that is adjacent to any other of the first, second, third, and fourth memory elements. 18. The radiation-tolerant FPGA switching element of claim 8, wherein: none of the first, second, third, and fourth memory elements is placed in a location that is within the double strike distance of any other of the first, second, third, and fourth memory elements. 19. The radiation-tolerant FPGA switching element of claim 8, further comprising: fifth and sixth switch transistors coupled in series between the first and second circuit nodes; a fifth memory element coupled to a control element of the fifth switch transistor; and a sixth memory element coupled to a control element of the sixth switch transistor. 20. The radiation-tolerant FPGA switching element of claim 19, wherein the first, second, third, fourth, fifth, and sixth memory elements each further comprise: an output node; a power node; a ground node; a first flash transistor coupled between the power node and the output node; and a second flash transistor coupled between the output node and the ground node. 21. The radiation-tolerant FPGA switching element of claim 19, wherein the first, second, third, fourth, fifth, and sixth memory elements each further comprise: an output node; a power node; a ground node; a standard load transistor coupled between the power node and the output node; and a flash transistor coupled between the output node and the ground node. 22. The radiation-tolerant FPGA switching element of claim 19, wherein the first, second, third, fourth, fifth, and sixth memory elements each further comprise: an output node; a power node; a ground node; a load resistor coupled between the power node and the output node; and a flash transistor coupled between the output node and the ground node. 23. The radiation-tolerant FPGA switching element of claim 19, wherein: the first, second, third, fourth, fifth, and sixth memory elements are SRAM cells. 24. The radiation-tolerant FPGA switching element of claim 19, wherein: each of the first, second, third, fourth, fifth, and sixth memory elements is part of an array of memory elements; and none of the first, second, third, fourth, fifth, and sixth memory elements is placed in the array of memory elements in a location that is adjacent to any other of the first, second, third, fourth, fifth, and sixth memory elements. 25. The radiation-tolerant FPGA switching element of claim 19, wherein: none of the first, second, third, fourth, fifth, and sixth memory elements is placed in a location that is within the double strike distance of any other of the first, second, third, fourth, fifth, and sixth memory elements. 26. The radiation-tolerant FPGA switching element of claim 8, wherein the memory transistors are n-channel transistors and the switch transistors are n-channel transistors. 27. The radiation-tolerant FPGA switching element of claim 8, wherein the memory transistors are p-channel transistors and the switch transistors are p-channel transistors.