IPC분류정보
국가/구분 |
United States(US) Patent
등록
|
국제특허분류(IPC7판) |
|
출원번호 |
UP-0218705
(2005-09-01)
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등록번호 |
US-7772115
(2010-08-30)
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발명자
/ 주소 |
|
출원인 / 주소 |
|
대리인 / 주소 |
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인용정보 |
피인용 횟수 :
6 인용 특허 :
25 |
초록
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A method for forming through-wafer interconnects (TWI) in a substrate of a thickness in excess of that of a semiconductor die such as a semiconductor wafer. Blind holes are formed from the active surface, sidewalls thereof are passivated and coated with a solder-wetting material. A vent hole is then
A method for forming through-wafer interconnects (TWI) in a substrate of a thickness in excess of that of a semiconductor die such as a semiconductor wafer. Blind holes are formed from the active surface, sidewalls thereof are passivated and coated with a solder-wetting material. A vent hole is then formed from the opposite surface (e.g., wafer back side) to intersect the blind hole. The blind hole is solder filled, followed by back thinning of the vent hole portion of the wafer to a final substrate thickness to expose the solder and solder-wetting material at both the active surface and the thinned back side. A metal layer such as nickel, having a glass transition temperature greater than that of the solder, may be plated to form a dam structure covering one or both ends of the TWI including the solder and solder-wetting material to prevent leakage of molten solder from the TWI during high temperature excursions. Intermediate structures of semiconductor devices, semiconductor devices and systems are also disclosed.
대표청구항
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What is claimed is: 1. A method for forming a plurality of through-wafer interconnects in a substrate, comprising: forming a plurality of blind holes into a substrate, each of the plurality of blind holes extending from a first surface to a respective blind end in the substrate; forming a plurality
What is claimed is: 1. A method for forming a plurality of through-wafer interconnects in a substrate, comprising: forming a plurality of blind holes into a substrate, each of the plurality of blind holes extending from a first surface to a respective blind end in the substrate; forming a plurality of vent holes extending into the substrate from a second surface wherein each vent hole of the plurality of vent holes at least partially intersects a respective blind hole of the plurality of blind holes; depositing a solder generally within each of the plurality of blind holes; thinning the substrate to a desired final thickness so as to at least remove the plurality of vent holes; and depositing a conductive material different from the solder over at least one end of the solder to form at least one dam structure for retaining the solder within the respective blind hole. 2. The method of claim 1, further comprising selecting the substrate to comprise a semiconductor material. 3. The method of claim 1, further comprising selecting the first surface to comprise an active surface. 4. The method of claim 1, further comprising providing at least one conductive bond pad on the first surface. 5. The method of claim 1, wherein forming the plurality of blind holes comprises at least one of laser drilling, laser ablation, dry etching, wet etching, and mechanical drilling. 6. The method of claim 1, further comprising forming each of the plurality of blind holes to a depth equal to or greater than the desired final thickness. 7. The method of claim 1, further comprising forming a mean diameter of the respective blind hole to be about 10 μm to about 150 μm. 8. The method of claim 1, further comprising depositing a solder-wetting material upon at least a portion of sidewalls of the plurality of blind holes, wherein the solder is deposited onto the solder-wetting material within each respective blind hole. 9. The method of claim 1, further comprising forming the plurality of vent holes by at least one of laser drilling, laser ablation, dry etching, wet etching, and mechanical drilling. 10. The method of claim 1, further comprising forming each vent hole of the plurality of vent holes to be substantially coaxially positioned with respect to the respective blind hole at least partially intersecting therewith. 11. The method of claim 1, further comprising forming each vent hole of the plurality of vent holes to exhibit a central axis oriented at an angle of up to about 45 degrees with respect to a central axis of the respective blind hole at least partially intersecting therewith. 12. The method of claim 1, further comprising forming each vent hole of the plurality of vent holes to have a lateral dimension equal to or greater than a lateral dimension of the respective blind hole at least partially intersecting therewith. 13. The method of claim 1, further comprising forming each vent hole of the plurality of vent holes to be substantially smaller in lateral dimension than the respective blind hole at least partially intersecting therewith. 14. The method of claim 1, further comprising depositing solder in the plurality of blind holes by one of drag soldering, hot air solder leveling, chemical vapor deposition, physical vapor deposition, and wave soldering. 15. The method of claim 1, wherein depositing the solder within each of the plurality of blind holes and onto the solder-wetting material therein, respectively comprises holding the first surface of the substrate in at least one of a vertical, near-vertical, and inverted orientation and against a flow of a molten solder. 16. The method of claim 1, wherein: depositing the solder generally within each of the plurality of blind holes comprises depositing a solder having a first glass transition temperature generally within each of the plurality of blind holes; and depositing the conductive material different from the solder over the at least one end of the solder to form the at least one dam structure for retaining solder within the respective blind hole comprises depositing a conductive material having a second glass transition temperature greater than the first glass transition temperature of the solder. 17. The method of claim 4, further comprising forming at least one blind hole of the plurality of blind holes to pass through the at least one conductive bond pad. 18. The method of claim 8, wherein depositing the solder-wetting material comprises depositing at least one of copper and nickel. 19. The method of claim 8, further comprising applying a metallic seed layer to the at least a portion of the sidewalls prior to depositing the solder-wetting material. 20. The method of claim 8, further comprising passivating the sidewalls of the plurality of blind holes prior to depositing the solder-wetting material. 21. The method of claim 8, wherein depositing the solder-wetting material upon at least a portion of the sidewalls of the plurality of blind holes comprises electroplating or electroless plating the sidewalls of the plurality of blind holes with a solder-wetting metal. 22. The method of claim 8, further comprising applying the solder-wetting material to a thickness of less than about 5 μm. 23. The method of claim 19, further comprising selecting the metallic seed layer to comprise one of tantalum and copper. 24. The method of claim 20, wherein passivating the sidewalls of the plurality of blind holes comprises oxidizing the sidewalls of the plurality of blind holes. 25. The method of claim 20, wherein passivating the sidewalls of the plurality of blind holes is effected by at least one of chemical vapor deposition and physical vapor deposition. 26. The method of claim 20, wherein passivating the sidewalls of the plurality of blind holes comprises depositing or forming at least one of silicon dioxide, silicon nitride, silicon oxynitride, BPSG, PSG, BSG, polyimide, and benzocyclobutene on the sidewalls of the plurality of blind holes. 27. The method of claim 15, further comprising selecting the near-vertical orientation to comprise an angle within 45 degrees of vertical. 28. The method of claim 15, further comprising changing the orientation of the first surface after application of the solder and reflowing the solder. 29. The method of claim 16, further comprising depositing another solder having a third glass transition temperature less than the second glass transition temperature of the conductive material over the at least one dam structure. 30. The method of claim 29, further comprising selecting the solder and the another solder to comprise different solder materials. 31. The method of claim 30, further comprising heating both the solder and the another solder to a temperature above a reflow temperature of each, and maintaining separation of the solder and the another solder with the at least one dam structure. 32. A method for forming at least one through-wafer interconnect in a substrate, comprising: providing a substrate having a first surface and a second surface; selecting a location for at least one through-wafer interconnect to pass through at least a portion of the substrate; forming a blind hole at the selected location from the first surface into the substrate to a selected depth; forming a passivating layer upon at least a portion of an interior of the blind hole; forming a seed layer over the passivation layer; forming a layer of a solder-wetting conductive material on the seed layer within the blind hole; forming a vent hole from the second surface to at least partially intersect the blind hole; substantially filling the blind hole with a solder having a first glass transition temperature; thinning the substrate from the second surface to a depth sufficient to at least remove the vent hole; and depositing another conductive material over at least one end of the solder and the seed layer to form a dam structure for retaining the solder within the blind hole, the other conductive material having a second glass transition temperature greater than the first glass transition temperature of the solder. 33. The method of claim 32, further comprising selecting the substrate to comprise a semiconductor material. 34. The method of claim 32, further comprising selecting the first surface to comprise an active surface. 35. The method of claim 32, further comprising providing at least one conductive bond pad on the first surface. 36. The method of claim 32, wherein forming the blind hole comprises at least one of laser drilling, laser ablation, dry etching, wet etching, and mechanical drilling. 37. The method of claim 32, further comprising selecting the seed layer to comprise one of tantalum and copper. 38. The method of claim 32, wherein depositing the seed layer comprises electroplating or electroless plating at least the portion of the interior of the blind hole with a solder-wetting metal. 39. The method of claim 32, wherein forming the vent hole comprises at least one of laser drilling, laser ablation, dry etching, wet etching, and mechanical drilling. 40. The method of claim 32, further comprising forming the vent hole to be substantially coaxially positioned with respect to the blind hole. 41. The method of claim 32, further comprising forming the vent hole to have a lateral dimension equal to or greater than a lateral dimension of blind hole. 42. The method of claim 32, further comprising forming the vent hole to be substantially smaller in lateral dimension than the blind hole. 43. The method of claim 32, wherein substantially filling the blind hole with the solder comprises one of drag soldering, hot air solder leveling, chemical vapor deposition, physical vapor deposition, and wave soldering. 44. The method of claim 32, wherein substantially filling the blind hole with the solder comprises holding the first surface of the substrate in at least one of a vertical, near-vertical, and inverted orientation and against a flow of a molten solder. 45. The method of claim 32, wherein depositing another conductive material over at least one end of the solder and the seed layer comprises plating the another conductive material. 46. The method of claim 32, wherein forming a passivation layer comprises oxidizing at least the portion of the interior of the blind hole. 47. The method of claim 32, wherein forming a passivation layer is effected by at least one of chemical vapor deposition and physical vapor deposition. 48. The method of claim 32, wherein forming a passivation layer comprises depositing or forming at least one of silicon dioxide, silicon nitride, silicon oxynitride, BPSG, PSG, BSG, polyimide, and benzocyclobutene. 49. The method of claim 32, further comprising depositing a further conductive material having a glass transition temperature less than the glass transition temperature of the another conductive material over the dam structure. 50. The method according to claim 33, further comprising selecting the substrate to comprise a semiconductor wafer having a first major surface comprising the first surface and containing a plurality of discrete integrated circuits. 51. The method of claim 35, further comprising forming the blind hole through the at least one conductive bond pad. 52. The method of claim 41, further comprising changing the orientation of the first surface after substantially filling the blind hole with solder and reflowing the solder. 53. The method of claim 44, further comprising selecting the near-vertical orientation to comprise an angle within 45 degrees of vertical. 54. The method according to claim 50, further comprising selecting the first major surface to include a plurality of conductive bond pads connected to the plurality of discrete integrated circuits. 55. The method according to claim 50, further comprising joining external electrical connectors to the dam structure to form one of a ball-grid-array package, a column grid array package, a leadless chip carrier, a quad flat pack and a quad flat no-lead package. 56. The method of claim 49, further comprising selecting the solder and the further conductive material to comprise different solder materials. 57. The method of claim 56, further comprising heating both the solder and the further conductive material to a temperature above a reflow temperature of each, and maintaining separation of the solder and the further conductive material with the dam structure.
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