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Methods for forming through-wafer interconnects, intermediate structures so formed, and devices and systems having at least one solder dam structure 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/44
출원번호 UP-0218705 (2005-09-01)
등록번호 US-7772115 (2010-08-30)
발명자 / 주소
  • Hiatt, W. Mark
출원인 / 주소
  • Micron Technology, Inc.
대리인 / 주소
    TraskBritt
인용정보 피인용 횟수 : 6  인용 특허 : 25

초록

A method for forming through-wafer interconnects (TWI) in a substrate of a thickness in excess of that of a semiconductor die such as a semiconductor wafer. Blind holes are formed from the active surface, sidewalls thereof are passivated and coated with a solder-wetting material. A vent hole is then

대표청구항

What is claimed is: 1. A method for forming a plurality of through-wafer interconnects in a substrate, comprising: forming a plurality of blind holes into a substrate, each of the plurality of blind holes extending from a first surface to a respective blind end in the substrate; forming a plurality

이 특허에 인용된 특허 (25)

  1. Kamperman James Steven ; Gall Thomas Patrick ; Stone David Brian, Cap providing flat surface for DCA and solder ball attach and for sealing plated through holes, multi-layer electronic.
  2. Kawakita, Yoshihiro; Andoh, Daizo; Echigo, Fumio; Nakamura, Tadashi, Circuit board having an interstitial inner via hole structure.
  3. Taniguchi,Osamu; Yamagishi,Yasuo; Omote,Koji, Circuit substrate and method for fabricating the same.
  4. Tee Onn Chong ; Chris Baldwin ; Chee-Yee Chung, Enhanced plated-through hole and via contact design.
  5. Lubert Kenneth J. ; Miller Curtis L. ; Miller Thomas R. ; Sebesta Robert D. ; Wilson James W. ; Wozniak Michael, Fine pitch circuitization with filled plated through holes.
  6. Lubert, Kenneth J.; Miller, Curtis L.; Miller, Thomas R.; Sebesta, Robert D.; Wilson, James W.; Wozniak, Michael, Fine pitch circuitization with filled plated through holes.
  7. Michael J. Cummings ; Michael V. Longo ; Curtis L. Miller ; Thomas R. Miller ; Michael Wozniak, Fine pitch circuitization with unfilled plated through holes.
  8. Gnadinger Alfred P. (Colorado Springs CO), High density data storage using stacked wafers.
  9. Wood,Alan G.; Doan,Trung Tri, Method for fabricating semiconductor component with thinned substrate having pin contacts.
  10. Brian Eugene Curcio ; Peter Alfred Gruber ; Frederic Maurer ; Konstantinos I. Papathomas ; Mark David Poliks, Method for filling high aspect ratio via holes in electronic substrates and the resulting holes.
  11. Hayakawa, Masao; Maeda, Takamichi; Oda, Mituwo, Method of making a through-hole connector.
  12. Kirby,Kyle K.; Akram,Salman; Hembree,David R.; Rigg,Sidney B.; Farnworth,Warren M.; Hiatt,William M., Microelectronic devices and methods for forming interconnects in microelectronic devices.
  13. Hayasaka, Nobuo; Okumura, Katsuya; Sasaki, Keiichi; Matsuo, Mie, Multichip semiconductor device, chip therefor and method of formation thereof.
  14. Hoffmeyer Mark Kenneth ; Isaacs Phillip Duane, Pad-on-via assembly technique.
  15. Hoffmeyer Mark Kenneth ; Isaacs Phillip Duane, Pad-on-via assembly technique.
  16. Booth Richard B. (Wappingers Falls NY) Gephard Robert H. (Poughkeepsie NY) Gremban Bradley S. (Lake Katrine NY) Poetzinger Janet E. (Rochester MN) Shen David T. (Poughkeepsie NY), Parallel process interposer (PPI).
  17. Sinha,Nishant, Process and integration scheme for fabricating conductive components, through-vias and semiconductor components including conductive through-wafer vias.
  18. Kang,Byoung Young, Semiconductor chip packages and methods for fabricating the same.
  19. Hara,Kazumi, Semiconductor chip, and semiconductor wafer including a variable thickness insulating layer.
  20. Umetsu, Kazushige; Amako, Jun; Yotsuya, Shinichi; Arakawa, Katsuji, Semiconductor chip, semiconductor device, circuit board and electronic equipment and production methods for them.
  21. Farnworth, Warren M.; Wood, Alan G.; Hembree, David R., Semiconductor component and interconnect having conductive members and contacts on opposing sides.
  22. Mashino, Naohiro; Higashi, Mitsutoshi, Semiconductor device and method of production of same.
  23. Murayama, Kei, Semiconductor device manufacturing method.
  24. Isaacs Phillip D. (Rochester MN) Knotts Gregg A. (Rochester MN) Swain Miles F. (Hayfield MN) Towne Burton A. (Austin MN), Solder ball connect pad-on-via assembly process.
  25. Parker, Jr., John L.; Miscikowski, Pamela L., Via connector and method of making same.

이 특허를 인용한 특허 (6)

  1. Yang, Chih-Chao; Edelstein, Daniel C.; Molis, Steven E., Enhanced diffusion barrier for interconnect structures.
  2. Yang, Chih-Chao; Edelstein, Daniel C.; Molis, Steven E., Enhanced diffusion barrier for interconnect structures.
  3. Kim, Woon-Chun; Yim, Soon-Gyu; Kweon, Young-Do; Lee, Jae-Kwang, Semiconductor package with a metal post.
  4. Kim, Woon-Chun; Yim, Soon-Gyu; Kweon, Young-Do; Lee, Jae-Kwang, Semiconductor package with a metal post and manufacturing method thereof.
  5. Juskey, Frank J.; Hartmann, Robert C., Wafer level package with embedded passive components and method of manufacturing.
  6. Goers, Uta-Barbara, Work pieces and methods of laser drilling through holes in substrates using an exit sacrificial cover layer.
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