IPC분류정보
국가/구분 |
United States(US) Patent
등록
|
국제특허분류(IPC7판) |
|
출원번호 |
UP-0965665
(2007-12-27)
|
등록번호 |
US-7772706
(2010-08-30)
|
발명자
/ 주소 |
- Balakrishnan, Sridhar
- Boyanov, Boyan
|
출원인 / 주소 |
|
대리인 / 주소 |
|
인용정보 |
피인용 횟수 :
6 인용 특허 :
5 |
초록
A spacer is adjacent to a conductive line. Vias that do not completely land on the conductive line land on the spacer and do not punch through into a volume below the spacer.
대표청구항
▼
We claim: 1. A method to make interconnects for a semiconductor die, comprising: forming a spacer adjacent a first conductive line, the spacer extending a distance from the first conductive line; forming a top dielectric layer on the spacer and first conductive line; forming an unlanded via hole th
We claim: 1. A method to make interconnects for a semiconductor die, comprising: forming a spacer adjacent a first conductive line, the spacer extending a distance from the first conductive line; forming a top dielectric layer on the spacer and first conductive line; forming an unlanded via hole that extends through the top dielectric layer to the first conductive line and the spacer, the spacer acting as an etch stop to prevent the via hole from extending below the spacer; and wherein the first conductive line has a first width within a selected distance of a desired area for the via hole to land and a second width less than the first width beyond the first distance; and wherein a second conductive line is spaced apart from the first conductive line, the spacer extends from the first conductive line to the second conductive line at locations where the first conductive line has the first width, and the spacer extends from the first conductive line but does not extend all the way to the second conductive line at locations where the first conductive line has the second width. 2. The method of claim 1, wherein forming the spacer comprises: forming a sacrificial layer on a bottom dielectric layer; forming the first conductive line; forming recesses in the sacrificial layer adjacent the first conductive line by removing portions of the sacrificial layer; forming a spacer layer on the recessed sacrificial layer and first conductive line; removing portions of the spacer layer from a top of the first conductive line and portions of a top surface of the recessed sacrificial layer, resulting in the spacers being on the sacrificial layer and adjacent the first conductive line; and removing at least a portion of the sacrificial layer. 3. The method of claim 1, wherein the first width is defined by a first line that extends laterally from a first side of the first conductive line to a second side of the first conductive line and beneath the via hole, and the first conductive line does not extend beyond the first width along the first line used to define the first width; the second width is defined by a second line that extends laterally from the first side of the first conductive line to the second side of the first conductive line and not beneath the via hole, and the first conductive line does not extend beyond the second width along the second line used to define the second width; and the first line is substantially the same distance from a substrate as the second line. 4. The method of claim 3, wherein the first line and the second line are substantially parallel to a substrate on which the first conductive line exists. 5. The method of claim 1, wherein the first conductive line has a long axis substantially parallel to a substrate, the first conductive line has the first width at a first position along the long axis and the first conductive line has the second width at a second position at a second position along the long axis, the second position being spaced apart from the first position. 6. The method of claim 1, wherein: the spacer is above an air gap; and forming an air gap comprises: forming a sacrificial layer on a bottom dielectric layer; forming the first conductive line; forming the spacer, wherein the spacer has an inner boundary adjacent the first conductive line and an outer boundary away from the first conductive line, at least a portion of the sacrificial layer beyond the outer boundary being exposed; and removing at least a portion of the sacrificial layer to leave behind the air gap. 7. A method to make interconnects of a semiconductor die, comprising: forming a first dielectric layer comprising a sacrificial material; patterning the first dielectric layer to form trenches; forming conductive lines in the trenches; recessing the first dielectric layer between the trenches; forming a layer of spacer material on the first dielectric layer in the recess and on the conductive lines; removing portions of the spacer layer from tops of the conductive lines and portions of tops of the first dielectric layer to expose the portions of the first dielectric layer, resulting in spacers adjacent to the conductive lines and on the first dielectric layer; removing portions of the first dielectric layer to result in a volume formerly occupied by the first dielectric layer that at least partially comprises air; wherein the exposed portions of the first dielectric layer are exposed at gaps between spacers, portions of the first dielectric layer are removed by decomposition, decomposition products being removed through gaps between spacers; forming a third dielectric layer on the conductive lines and spacers; forming vias through the third dielectric layer, at least one of the vias landing partially on a first one of the conductive lines and partially on a first one of the spacers; wherein at least a first conductive line of the conductive lines has a first width adjacent a first via of the formed vias and a second width less than the first width a distance away from the first via; and wherein a second conductive line of the conductive lines is spaced laterally apart from the first conductive line, a first spacer of the spacers extends from the first conductive line to the second conductive line at locations between the first via and the portions of the second conductive line closest to the first via, and wherein there are other locations adjacent to where the first conductive line has the second width where the first spacer extends from the first conductive line but does not extend all the way to the second conductive line. 8. The method of claim 7, wherein substantially all of the first dielectric layer is removed. 9. The method of claim 7, wherein the first dielectric layer comprises a porous material and a porogen material, and wherein at least some of the porogen material is removed. 10. The method of claim 7, wherein forming vias through the third dielectric layer comprises: etching the third dielectric layer to form a via hole through the third dielectric layer, wherein the etchant used to form the via hole etches the third dielectric layer at a faster rate than it etches the spacer so that the spacer acts as an etch stop layer. 11. The method of claim 10, wherein the first dielectric layer comprises a sacrificial material, further comprising removing portions of the first dielectric layer to result in a volume formerly occupied by the first dielectric layer that at least partially comprises air, and wherein the spacer prevents the via hole from punching through to the volume formerly occupied by the first dielectric layer. 12. The method of claim 7, wherein the gaps between spacers are exposed to the environment and are not covered with another dielectric layer while portions of the first dielectric layer are removed. 13. The method of claim 7, wherein the first conductive line has a long axis substantially parallel to a substrate, the first conductive line has the first width at a first position along the long axis and the first conductive line has the second width at a second position at a second position along the long axis, the second position being spaced apart from the first position. 14. A semiconductor die with interconnects, comprising: a first conductive line; a first spacer adjacent to the first conductive line; a first dielectric layer on the first conductive line; a first via through the first dielectric layer to the first conductive line, the first via being an unlanded via that extends beyond the first conductive line onto the first spacer; wherein the first conductive line has a first width adjacent the via and a second width less than the first width a distance away from the via; and wherein a second conductive line is spaced apart from the first conductive line, the spacer extends from the first conductive line to the second conductive line at locations where the first conductive line has the first width, and the spacer extends from the first conductive line but does not extend all the way to the second conductive line at locations where the first conductive line has the second width. 15. The method of claim 14, wherein the first width is defined by a first line that extends laterally from a first side of the conductive line to a second side of the conductive line and beneath the via, and the conductive line does not extend beyond the first width along the first line used to define the first width; the second width is defined by a second line that extends laterally from the first side of the conductive line to the second side of the conductive line and not beneath the via, and the conductive line does not extend beyond the second width along the second line used to define the second width; and the first line is substantially the same distance from a substrate as the second line. 16. The method of claim 14, wherein the conductive line has a long axis substantially parallel to a substrate, the conductive line has the first width at a first position along the long axis and the conductive line has the second width at a second position at a second position along the long axis, the first position being under the via, the second position being spaced apart from the first position. 17. A method to make interconnects for a semiconductor die, comprising: forming a spacer adjacent a conductive line, the spacer extending a distance from the conductive line; forming a top dielectric layer on the spacer and conductive line; forming an unlanded via hole that extends through the top dielectric layer to the conductive line and the spacer, the spacer acting as an etch stop to prevent the via hole from extending below the spacer; and wherein the conductive line has a first width within a selected distance of a desired area for the via hole to land and a second width less than the first width beyond the first distance; and wherein a second conductive line is spaced laterally apart from the conductive line, the spacer extends from the conductive line to the second conductive line at locations between the unlanded via hole and the portions of the second conductive line closest to the unlanded via hole, and wherein there are other locations adjacent where the conductive line has the second width where the spacer extends from the conductive line but does not extend all the way to the second conductive line.
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