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A semiconductor component includes a thinned semiconductor substrate having protective polymer layers on up to six surfaces. The component also includes contacts on a circuit side of the substrate, conductive vias in electrical contact with the contacts, and conductors on a backside of the substrate

A semiconductor component includes a thinned semiconductor substrate having protective polymer layers on up to six surfaces. The component also includes contacts on a circuit side of the substrate, conductive vias in electrical contact with the contacts, and conductors on a backside of the substrate. A method for fabricating the component includes the steps of providing the semiconductor substrate with the contacts on the circuit side, forming conductive vias from the back side in electrical contact with the contacts, and forming conductors on the backside.

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We claim: 1. A method for fabricating a semiconductor component comprising: providing a semiconductor wafer comprising a plurality of semiconductor dice separated by streets, each semiconductor die comprising a substrate having a circuit side with integrated circuits, a back side and a plurality of

We claim: 1. A method for fabricating a semiconductor component comprising: providing a semiconductor wafer comprising a plurality of semiconductor dice separated by streets, each semiconductor die comprising a substrate having a circuit side with integrated circuits, a back side and a plurality of contacts on the circuit side in electrical communication with the integrated circuits having a first pattern; forming a circuit side polymer layer on the dice and a plurality of polymer filled trenches in the streets; forming a plurality of conductive vias from the backside through the substrate and the contacts in electrical contact with the contacts; forming a plurality of conductors on the backside in electrical communication with the conductive vias configured to redistribute and fan out the first pattern to a second pattern; forming a back side polymer layer on the dice; forming a plurality of terminal contacts on the back side having the second pattern in electrical communication with the conductors; and singulating the wafer through the polymer filled trenches such that each die is encapsulated on six surfaces by polymer layers. 2. The method of claim 1 further comprising thinning the substrate from the backside prior to the forming the conductors step. 3. The method of claim 1 wherein the forming the conductors step comprises depositing and etching a redistribution layer on the back side. 4. The method of claim 1 wherein the second pattern comprises a grid array. 5. The method of claim 1 wherein the forming the conductive vias step comprises laser machining. 6. The method of claim 1 wherein the forming the conductive vias step comprises etching. 7. The method of claim 1 wherein the forming the conductive vias step forms a plurality of conductive vias having a first pitch, and the forming the conductor step forms a plurality of conductors having a second pitch greater than the first pitch. 8. The method of claim 1 wherein the terminal contacts comprise balls and the second pattern comprises a ball grid array (BGA) or a fine ball grid array (FBGA). 9. The method of claim 1 wherein the forming the conductors step comprises a process selected from the group consisting of a plating process, an electrolytic process and an electroless process. 10. A method for fabricating a semiconductor component comprising: providing a semiconductor wafer comprising a plurality of semiconductor dice separated by streets, each semiconductor die comprising a substrate having a circuit side with integrated circuits, a back side and a plurality of contacts on the circuit side in a pattern in electrical communication with the integrated circuits; forming a circuit side polymer layer on the dice and a plurality of polymer filled trenches in the streets; forming a plurality of conductive vias through the substrate from the backside to the circuit side in electrical contact with the contacts; thinning the substrate from the backside; forming a plurality of back side conductors on the backside in electrical communication with the conductive vias configured to redistribute and fan out the pattern of the contacts to a grid array; forming a back side polymer layer on the dice; forming a plurality of terminal contacts on the back side in the grid array in electrical communication with the conductors; and singulating the wafer through the polymer filled trenches such that each die is encapsulated on six surfaces by polymer layers. 11. The method of claim 10 wherein the terminal contacts comprise balls and the grid array comprises a ball grid array (BGA) or a fine ball grid array (FBGA). 12. The method of claim 10 wherein the forming the back side conductors step comprises depositing and etching a redistribution layer on the backside. 13. The method of claim 10 wherein the forming the conductive vias step comprises counterboring from the back side to a selected depth. 14. The method of claim 10 wherein the forming the conductive vias step comprises providing conductivity regions in electrical contact with the electrical conductors and counterboring from the back side to the conductivity regions.