IPC분류정보
국가/구분 |
United States(US) Patent
등록
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국제특허분류(IPC7판) |
|
출원번호 |
UP-0514601
(2006-08-31)
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등록번호 |
US-7776765
(2010-09-06)
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발명자
/ 주소 |
- Forbes, Leonard
- Ahn, Kie Y.
- Bhattacharyya, Arup
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출원인 / 주소 |
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대리인 / 주소 |
Schwegman, Lundberg & Woessner, P.A.
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인용정보 |
피인용 횟수 :
2 인용 특허 :
194 |
초록
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Electronic apparatus and methods of forming the electronic apparatus include a tantalum silicon oxynitride film on a substrate for use in a variety of electronic systems. The tantalum silicon oxynitride film may be structured as one or more monolayers. The tantalum silicon oxynitride film may be for
Electronic apparatus and methods of forming the electronic apparatus include a tantalum silicon oxynitride film on a substrate for use in a variety of electronic systems. The tantalum silicon oxynitride film may be structured as one or more monolayers. The tantalum silicon oxynitride film may be formed using atomic layer deposition. Metal electrodes may be disposed on a dielectric containing a tantalum silicon oxynitride film.
대표청구항
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What is claimed is: 1. A method comprising: forming a dielectric layer on a substrate, the dielectric layer including a layer of TaSiON, the layer of TaSiON formed using atomic layer deposition including: forming a layer of TaN by atomic layer deposition; forming a layer of SiN by atomic layer depo
What is claimed is: 1. A method comprising: forming a dielectric layer on a substrate, the dielectric layer including a layer of TaSiON, the layer of TaSiON formed using atomic layer deposition including: forming a layer of TaN by atomic layer deposition; forming a layer of SiN by atomic layer deposition; annealing the layer of TaN with the layer of SiN; oxidizing the layers of TaN and SiN to form TaSiON; and forming a metal gate on and contacting the dielectric layer. 2. The method of claim 1, wherein forming the metal gate includes forming a gate of a silicon MOSFET. 3. The method of claim 1, wherein forming the metal gate includes forming a gate of a germanium MOSFET. 4. The method of claim 1, wherein forming the metal gate includes forming a gate of a SiGe MOSFET. 5. The method of claim 1, wherein the method includes forming the dielectric layer structured as a tunnel gate insulator in a flash memory and the metal gate structured as a floating gate in the flash memory. 6. The method of claim 1, wherein the method includes forming the dielectric layer structured as an inter-gate insulator in a flash memory and the metal gate structured as a control gate in the flash memory. 7. The method of claim 1, wherein the method includes forming the dielectric layer structured as a nanolaminate dielectric in a flash memory. 8. The method of claim 1, wherein forming a metal gate includes forming the metal gate formed by atomic layer deposition. 9. The method of claim 1, wherein forming a metal gate includes forming the metal gate by substituting a desired metal material for a previously disposed substitutable material. 10. The method of claim 1, wherein forming a metal gate includes forming a self aligned metal gate on and contacting the dielectric layer. 11. The method of claim 1, wherein the annealing and the oxidizing are performed together. 12. The method of claim 1, wherein the layer of TaN and the layer of SiN are annealed and oxidized by rapid thermal oxidation to form TaSiON. 13. The method of claim 1, wherein the method includes forming a plurality of alternating layers of TaN and SiN prior to annealing. 14. The method of claim 1, wherein the layer of TaN is formed by atomic layer deposition including: forming a layer of tantalum using a tantalum precursor; and forming TaN using a nitrogen reactant precursor. 15. The method of claim 14, wherein the tantalum precursor is Ta(OC2H5)5. 16. The method of claim 14, wherein the tantalum precursor is TaCl5. 17. The method of claim 14, wherein hydrogen is pulsed with the tantalum precursor. 18. The method of claim 14, wherein the nitrogen reactant precursor is nitrogen. 19. The method of claim 14, wherein the nitrogen reactant precursor is ammonia. 20. The method of claim 14, wherein the nitrogen reactant precursor is butylamine. 21. The method of claim 14, wherein the nitrogen reactant precursor is allylamine. 22. The method of claim 14, wherein the nitrogen reactant precursor is dimethylhydrazine. 23. The method of claim 14, wherein the nitrogen reactant precursor is exposed at a temperature ranging from 400 degrees Celsius and 500 degrees Celsius. 24. A method comprising: forming a dielectric layer on a substrate, the dielectric layer including a layer of TaSiON, the layer of TaSiON formed using atomic layer deposition; and forming a self aligned metal electrode on and contacting the dielectric layer using a previously disposed sacrificial carbon layer on the dielectric layer and sacrificial carbon sidewall spacers adjacent to the sacrificial carbon layer. 25. The method of claim 24, wherein forming a self aligned metal electrode includes: forming a sacrificial carbon gate on the dielectric layer; forming sacrificial carbon sidewall spacers adjacent to the sacrificial carbon gate; forming source/drain regions for a transistor using the sacrificial carbon sidewall spacers to define the source/drain regions; replacing the sacrificial carbon sidewall spacers with non-carbon sidewall spacers; and replacing the sacrificial carbon gate with a desired metal gate material. 26. The method of claim 25, wherein replacing the sacrificial carbon sidewall spacers with non-carbon sidewall spacers includes performing a plasma oxidation process to remove the carbon sidewall spacers. 27. The method of claim 26, wherein replacing the sacrificial carbon gate with a desired metal gate material includes replacing the sacrificial carbon gate with one or more materials from a group consisting of aluminum, tungsten, molybdenum, gold, alloys of gold, silver, alloys of silver, platinum, rhenium, ruthenium, rhodium, nickel, osmium, palladium, iridium, cobalt, and germanium. 28. A method comprising: forming an array of memory cells on a substrate, each memory cell including a dielectric layer having a layer of TaSiON, wherein forming each memory cell includes: forming the layer of TaSiON using atomic layer deposition; and forming a metal electrode on and contacting the dielectric layer, wherein forming the layer of TaSiON includes: forming a layer of TaN by atomic layer deposition; forming a layer of SiN by atomic layer deposition; annealing the layer of TaN with the layer of SiN; and oxidizing the layers of TaN and the SiN to form TaSiON. 29. The method of claim 28, wherein forming a metal electrode includes: forming a layer of substitutable material on the dielectric layer; and substituting a desired metal material for the substitutable material to provide the metal gate on the dielectric layer. 30. The method of claim 29, wherein forming a layer of substitutable material includes forming a structure having one of more materials of a group consisting of carbon, polysilicon, germanium, and silicon-germanium. 31. The method of claim 29, wherein substituting a desired metal material for the substitutable material includes substituting for the carbon structure one or more materials from the group consisting of aluminum, gold, silver, a gold alloy, a silver alloy, copper, platinum, rhenium, ruthenium, rhodium, nickel, osmium, palladium, iridium, and cobalt. 32. A method comprising: forming an array of memory cells on a substrate, each memory cell including a dielectric layer having a layer of TaSiON, wherein forming each memory cell includes: forming the layer of TaSiON using atomic layer deposition; and forming a metal electrode on and contacting the dielectric layer, wherein the metal gate is formed as the metal gate of a transistor, the metal gate formed by: forming a sacrificial carbon gate on the dielectric layer; forming sacrificial carbon sidewall spacers adjacent to the sacrificial carbon gate; forming source/drain regions for the transistor using the sacrificial carbon sidewall spacers to define the source/drain regions; replacing the sacrificial carbon sidewall spacers with non-carbon sidewall spacers; and replacing the sacrificial carbon gate with a desired metal gate material to provide the desired metal gate material on the gate dielectric. 33. The method of claim 32, wherein replacing the sacrificial carbon gate with a desired metal gate material includes replacing the sacrificial carbon gate with one or more materials from a group consisting of aluminum, tungsten, molybdenum, gold, alloys of gold, silver, alloys of silver, platinum, rhenium, ruthenium, rhodium, nickel, osmium, palladium, iridium, cobalt, and germanium. 34. A method comprising: providing a controller; and coupling a transistor to the controller, the transistor having a metal gate disposed on a dielectric layer on a substrate for an integrated circuit, the dielectric layer having a layer of TaSiON, the layer of TaSiON formed using atomic layer deposition, wherein the layer of TaSiON formed using atomic layer deposition includes: forming a layer of TaN by atomic layer deposition; forming a layer of SiN by atomic layer deposition; annealing the layer of TaN with the layer of SiN; and oxidizing the layers of TaN and the SiN to form TaSiON. 35. The method of claim 34, wherein the metal gate is formed by atomic layer deposition. 36. The method of 34, wherein the metal gate is formed by substituting a desired metal material for previously disposed substitutable material. 37. A method comprising: providing a controller; and coupling a transistor to the controller, the transistor having a metal gate disposed on a dielectric layer on a substrate for an integrated circuit, the dielectric layer having a layer of TaSiON, the layer of TaSiON formed using atomic layer deposition, wherein the metal gate is formed by forming a self aligned metal gate on and contacting the dielectric layer using a previously disposed sacrificial carbon gate on the dielectric layer and sacrificial carbon sidewall spacers adjacent to the sacrificial carbon gate. 38. The method of claim 37, wherein providing a controller includes providing a processor. 39. The method of claim 37, wherein the method includes forming an information handling system. 40. The method of claim 39, wherein forming an information handling system includes forming a portable wireless device.
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