Multi-processor reconfigurable computing system
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
G06F-003/00
G06F-005/00
G06F-015/76
출원번호
UP-0195409
(2005-08-02)
등록번호
US-7779177
(2010-09-06)
발명자
/ 주소
Chow, Paul
출원인 / 주소
Arches Computing Systems
대리인 / 주소
Currier, T Andrew
인용정보
피인용 횟수 :
0인용 특허 :
17
초록▼
A reconfigurable multi-processor computing system including a plurality of configurable processing elements each having a plurality of integrated high-speed serial input/output ports. Interconnects link the plurality of processing elements, wherein at least one of the integrated high-speed serial in
A reconfigurable multi-processor computing system including a plurality of configurable processing elements each having a plurality of integrated high-speed serial input/output ports. Interconnects link the plurality of processing elements, wherein at least one of the integrated high-speed serial input/output ports of each processing element is connected by at least one interconnect to at least one of the integrated high-speed serial input/output ports of each other processing element, thereby creating a full mesh network. The full mesh network is located on a processor card, multiples of which may be grouped in a shelf having a backplane card with a shelf controller card for providing cross-connects between processor cards. Multiple shelves may be interconnected to form a large computer system.
대표청구항▼
What is claimed is: 1. A configurable computing system, comprising: a plurality of configurable processing elements each having a plurality of integrated high-speed serial input/output ports; and interconnects between the plurality of processing elements, at least one of the integrated high-speed s
What is claimed is: 1. A configurable computing system, comprising: a plurality of configurable processing elements each having a plurality of integrated high-speed serial input/output ports; and interconnects between the plurality of processing elements, at least one of the integrated high-speed serial input/output ports of each processing element is connected by at least one interconnect to at least one of the integrated high-speed serial input/output ports of each other processing element forming a processing card, and at least one of the configurable processing elements in the processing card having one or more of its integrated high-speed serial input/output ports for connecting to other processing cards. 2. The computing system claimed in claim 1, wherein said interconnects and said processing elements form a full mesh network. 3. The computing system claimed in claim 1, wherein said interconnects directly connect respective integrated high-speed serial input/output ports. 4. The computing system claimed in claim 3, wherein said interconnects comprise a signal path chosen from the group including an electrical path, an optical path, and an RF transmission link. 5. The computing system claimed in claim 3, wherein one integrated high-speed serial output port and one integrated high-speed serial input port on each processing element are connected to corresponding integrated high-speed serial input and output ports, respectively, on each other processing element by parallel electrical traces, and wherein the interconnected processing elements utilize differential signalling. 6. The computing system claimed in claim 1, wherein each of said plurality of configurable processing elements comprises a programmable logic device for implementing digital circuits. 7. The computing system claimed in claim 6, wherein said programmable logic devices comprise field programmable logic devices. 8. The computing system claimed in claim 7, wherein said integrated high-speed serial input/output ports of said field programmable logic devices each include an integrated serializer/deserializer transceiver and clock data recovery circuitry. 9. The computing system claimed in claim 1, wherein said processing elements and said interconnects are disposed upon a common substrate, and wherein one of said processing elements comprises a processor card control block for routing communications between said substrate and other substrates, said processor card control block including a plurality of card-level high-speed serial input/output ports for sending and receiving said communications. 10. The computing system claimed in claim 9, wherein said processor card control block includes one of said processing elements and a processor module connected by a bus. 11. The computing system claimed in claim 9, including a shelf containing a plurality of said substrates, and a backplane card for interconnecting said plurality of substrates, said backplane card including interconnectors for connecting to said card-level high-speed serial input/output ports and including a shelf control card, wherein said shelf control card provides reconfigurable cross-connects between said substrates. 12. The computing system claimed in claim 11, further including a plurality of said shelves and a system-level switch card for interconnecting said shelves. 13. The computing system claimed in claim 1, further including one or more local memory blocks connected to one of said processing elements to form a processing node. 14. A configurable processing card, comprising: a plurality of configurable processing means for implementing digital logic circuits based upon configuration instructions, wherein said processing means includes a plurality of integrated input/output means for high-speed output serialization and input deserialization of data; and interconnection means between the plurality of processing means for connecting at least one of the integrated input/output means on each processing means with at least one integrated input/output means of each other processing means forming a processing card, and at least one of the configurable processing elements in the processing cards having one or more of its integrated high-speed serial input/output means for connecting to other processing cards. 15. The processing card claimed in claim 14, wherein said interconnection means and said processing means form a full mesh network. 16. The processing card claimed in claim 14, wherein one integrated input means and one integrated output means on each processing means are connected to corresponding integrated input means and integrated output means, respectively, on each other processing means by parallel electrical traces, and wherein the interconnected processing means utilize differential signalling. 17. The processing card claimed in claim 14, wherein said integrated input/output means each include an integrated serializer/deserializer transceiver means and clock data recovery means. 18. The processing card claimed in claim 15, wherein said full mesh network of processing means and said interconnection means are disposed upon a substrate, and wherein one of said processing means includes means for routing communications between said substrate and other substrates. 19. A processing shelf, comprising a plurality of said substrates as claimed in claim 18, each having one of said full mesh networks, and a backplane card for interconnecting said plurality of substrates, said backplane card including interconnection means for connecting to said means for routing communications. 20. The computer system comprising a plurality of shelves as claimed in claim 19 and a system-level switch card for interconnecting said shelves.
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이 특허에 인용된 특허 (17)
Huberman Bernardo A. (Palo Alto CA) Hogg Tad H. (Anchorage AK), Adaptive self-repairing processor array.
Casselman Steven Mark (Reseda CA), FPGA virtual computer for executing a sequence of program instructions by successively reconfiguring a group of FPGA in.
Barker Thomas Norman ; Collins Clive Allan ; Dapp Michael Charles ; Dieffenderfer James Warren ; Knowles Billy Jack ; Lesmeister Donald Michael ; Miles Richard Ernest ; Nier Richard Edward ; Richards, Fully distributed processing memory element.
Cypher Robert E. (Los Gatos CA) Sanz Jorge L. C. (Los Gatos CA), Hierarchical interconnection network architecture for parallel processing, having interconnections between bit-addressib.
Gilson Kent L. (255 N. Main St. ; Apt. 210 Salt Lake City UT 84115), Integrated circuit computing device comprising a dynamically configurable gate array having a microprocessor and reconfi.
Gilson Kent L. (Salt Lake City UT), Integrated circuit computing device comprising a dynamically configurable gate array having a microprocessor and reconfi.
Hillis W. Daniel (111 Ivy St. Brookline MA 02146) Knight ; Jr. Thomas F. (58 Douglas Rd. Belmont MA 02178) Bawden Alan (93 Jackson St. Cambridge MA 02140) Kahle Brewster L. (59 Munroe St. Somerville , Parallel processor/memory circuit.
Gorin Allen L. (Fair Lawn NJ) Makofsky Patrick A. (Randolph NJ) Morton Nancy (Dover NJ) Oliver Neal C. (Madison NJ) Shively Richard R. (Convent Station NJ) Stanziola Christopher A. (Hyde Park NY), Reconfigurable signal processor.
Tulpule Bhalchandra R. (Farmington CT) Collins Robert E. (East Hartford CT) Binnall Daniel G. (Simsbury CT), n-Dimensional modular multiprocessor lattice architecture.
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