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The invention provides a method and system for operating a pipelined microprocessor more quickly, by detecting instructions that load from identical memory locations as were recently stored to, without having to actually compute the referenced external memory addresses. The microprocessor examines t

The invention provides a method and system for operating a pipelined microprocessor more quickly, by detecting instructions that load from identical memory locations as were recently stored to, without having to actually compute the referenced external memory addresses. The microprocessor examines the symbolic structure of instructions as they are encountered, so as to be able to detect identical memory locations by examination of their symbolic structure. For example, in a preferred embodiment, instructions that store to and load from an identical offset from an identical register are determined to be referencing the identical memory location, without having to actually compute the complete physical target address.

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The invention claimed is: 1. A pipelined microprocessor detecting a first instruction using first base and offset address values to load data from a first memory location that was previously stored to by an instruction using identical base and offset values, wherein the first instruction is detecte

The invention claimed is: 1. A pipelined microprocessor detecting a first instruction using first base and offset address values to load data from a first memory location that was previously stored to by an instruction using identical base and offset values, wherein the first instruction is detected based upon the first base and offset address values and without computing a memory address equaling the first base address value added to the offset address value in detecting the first instruction. 2. A pipelined microprocessor as claimed in claim 1 wherein the pipelined microprocessor detects a second instruction using second base and offset address values to store data into a second memory location that was previously read from, wherein the second instruction is detected based upon the second base and offset address values and without computing a memory address equaling the second base address value added to the offset address value in detecting the second instruction. 3. A pipelined microprocessor as claimed in claim 1 wherein the pipelined microprocessor examines base and offset address values used to access memory locations by store instructions that store data into the memory locations, and detects load instructions that load data from memory locations corresponding to base and offset address values identical to the base and offset address values used by the store instructions. 4. A pipelined microprocessor as claimed in claim 2 wherein the pipelined microprocessor examines base and offset address values used to access memory locations by load instructions that load data from the memory locations, and detects store instructions that store data into memory locations corresponding to base and offset address values identical to the base and offset address values used by the load instructions. 5. A pipelined microprocessor as claimed in claim 3 wherein the pipelined microprocessor detects identical offset address values and identical base address values in at least one register within the pipelined microprocessor. 6. A pipelined microprocessor as claimed in claim 4 wherein the pipelined microprocessor detects identical offset address values and identical base address values in at least one register within the pipelined microprocessor. 7. A pipelined microprocessor as claimed in claim 6 wherein the pipelined microprocessor comprises: an instruction decode stage detecting load instructions that load data from memory locations corresponding to offset address values from an identical and base address values identical to offset address values and base address values used by prior store instructions that store data into the memory locations; and a bypass element sending a bypass signal to an instruction execution stage of the pipelined microprocessor that indicates that a load instruction uses a base address value and an offset address value identical to a base address value and an offset address value used by a prior store instruction. 8. A pipelined microprocessor as claimed in claim 4 wherein the pipelined microprocessor comprises: an instruction decode stage detecting store instructions that store data into memory locations using offset address values and base address values identical to offset address values and base address values used by prior load instructions that load data from memory locations; and a bypass element sending a bypass signal to an instruction execution stage of the pipelined microprocessor that indicates that a store instruction uses a base address value and an offset address value identical to a base address value and an offset address value used by a prior load instruction. 9. A method for operating a pipelined microprocessor, comprising: detecting, in the pipelined microprocessor, a first instruction using first base and offset address values to load data from a first memory location that was previously stored to by an instruction using identical base and offset values, wherein the first instruction is detected based upon the first base and offset address values and without computing a memory address equaling the first base address value added to the offset address value in detecting the first instruction. 10. A method for operating a pipelined microprocessor as claimed in claim 9, further comprising: detecting, in the pipelined microprocessor, a second instruction using second base and offset address values to store data into a second memory location that was previously read from, wherein the second instruction is detected based upon the second base and offset address values and without computing a memory address equaling the second base address value added to the offset address value in detecting the second instruction. 11. A method for operating a pipelined microprocessor as claimed in claim 9, further comprising; examining, in the pipelined microprocessor, base and offset address values used to access memory locations by store instructions that store data into the memory locations; and detecting load instructions that load data from memory locations corresponding to base and offset address values identical to the base and offset address values used by the store instructions. 12. A method for operating a pipelined microprocessor as claimed in claim 10, further comprising: examining, in the pipelined microprocessor, base and offset address values used to access memory locations by load instructions that load data from memory locations; and detecting said instructions that store data into memory locations corresponding to base and offset address values identical to the base and offset address values used by the load instructions. 13. A method for operating a pipelined microprocessor as claimed in claim 11, further comprising: detecting, in an instruction decode stage of the pipelined microprocessor, load instructions that load data from memory locations corresponding to offset address values and base address values identical to offset address values and base address values used by prior store instructions that store data into the memory locations; and sending a bypass signal from a bypass element to an instruction execution stage of the pipelined microprocessor, wherein the bypass signal indicates that a load instruction uses a base address value and an offset address value identical to a base address value and an offset address value used by a prior store instruction. 14. A method for operating a pipelined microprocessor as claimed in claim 12, further comprising: detecting, in an instruction decode stage of the pipelined microprocessor, store instructions that store data into memory locations using offset address values and base address values identical to offset address values and base address values used by prior load instructions that load data from memory locations; and sending a bypass signal from a bypass element to an instruction execution stage of the pipelined microprocessor, wherein the bypass signal indicates that a load instruction uses a base address value and an offset address value identical to a base address value and an offset address value used by a prior store instruction. 15. A method for operating a pipelined microprocessor, comprising; detecting a first instruction that stores data to a first memory location, the first instruction comprising syntax for computing an effective address for the first memory location; detecting a second instruction that loads data from a second memory location, the second instruction comprising syntax for computing an effective address for said second memory location; determining the syntax for the first instruction and the syntax for the second instruction; using the syntax for the first instruction and the syntax for the second instruction to determine a relationship between the first memory location and the second memory location, without using the effective address of the first memory location or the effective address of the second memory location to determine the relationship between the first memory location and the second memory location; and using the relationship to determine whether to perform one of the first instruction and the second instruction. 16. A method for operating a pipelined microprocessor as claimed in claim 15, wherein the syntax for the first instruction and the syntax for the second instruction refer to an identical memory location.