초록 ▼

A system, structure and method is provided for providing dynamic optimization of integrated circuits using a non-contact method of selection, and a design structure on which a subject circuit resides. The method is provided for optimizing an electronic system having at least one integrated circuit.

A system, structure and method is provided for providing dynamic optimization of integrated circuits using a non-contact method of selection, and a design structure on which a subject circuit resides. The method is provided for optimizing an electronic system having at least one integrated circuit. The method includes storing a target performance voltage of the at least one integrated circuit; remotely querying the at least one integrated circuit to obtain the target performance voltage; and providing an operational voltage of a next-level assembly according to the stored target performance voltage.

대표청구항 ▼

It is claimed: 1. A method of optimizing an electronic system having at least one integrated circuit, the method comprising: storing a target performance voltage of the at least one integrated circuit in an identification circuit; remotely querying the identification circuit associated with the at

It is claimed: 1. A method of optimizing an electronic system having at least one integrated circuit, the method comprising: storing a target performance voltage of the at least one integrated circuit in an identification circuit; remotely querying the identification circuit associated with the at least one integrated circuit to obtain the target performance voltage of the at least one integrated circuit; and providing an operational voltage of a next-level assembly according to the stored target performance voltage of the at least one integrated circuit. 2. The method of claim 1, wherein the target performance voltage is within an optimal supply voltage range for the at least one integrated circuit. 3. The method of claim 1, wherein the at least one integrated circuit is a batch of integrated circuits, various of which are of different technologies, wherein the method further comprises: testing at least two integrated circuits of the batch of integrated circuits to determine the target performance voltage for each of the at least two integrated circuits; storing the target performance voltage for each of the at least two integrated circuits on each of the integrated circuits; querying each of the integrated circuits for the target performance voltage; and providing the target performance voltage in order to determine that the at least two integrated circuits are compatible for assembly. 4. The method of claim 1, wherein the remotely querying the at least one integrated circuit for the target performance voltage includes querying a radio frequency unit on the at least one integrated circuit by use of RFID technology. 5. The method of claim 1, wherein the storing is provided in a non-volatile memory integrated with the integrated circuit. 6. The method of claim 1, further comprising optimizing an operational voltage or power consumption of the electronic system by using compatible integrated circuits based on compatible operational voltages obtained from the target performance voltage of each of the at least one integrated circuit. 7. The method of claim 1, wherein the storing includes storing a representation of the target performance voltage in a storage unit of the integrated circuit. 8. The method of claim 1, wherein the storing includes programming a non-volatile memory of the at least one integrated circuit with the target performance voltage. 9. The method of claim 1, further comprising testing the at least one integrated circuit until the target performance voltage is achieved. 10. The method of claim 9, wherein the achieving includes incrementing or decrementing a voltage of the at least one integrated circuit to reach the target performance voltage. 11. The method of claim 10, further comprising determining whether the voltage is at a minimum voltage or a maximum voltage, wherein if the at least one integrated circuit is not at a minimum voltage, decrementing the voltage of the at least one integrated circuit; and if the at least one integrated circuit is not at a maximum voltage, incrementing the voltage of the at least one integrated circuit. 12. The method of claim 1, further comprising manufacturing the at least one integrated circuit with a functional unit, a performance monitoring unit, a storage unit and a radio frequency identification unit. 13. The method of claim 1, wherein non-volatile storage stores integrated circuit process characteristics obtained from a performance testing unit for the at least one integrated circuit. 14. The method of claim 13, wherein the characteristics for the at least one integrated circuit include voltage, temperature and processing bias. 15. The method of claim 14, wherein the characteristics for the at least one integrated circuit include nominal performance points including a matrix of voltages at different temperatures, at any required or desired granularity. 16. The method of claim 14, wherein the characteristics are relayed to an assembler or downstream manufacturer via RFID. 17. The method of claim 13, Wherein the performance testing unit is a ring oscillator. 18. The method of claim 1, further comprising providing performance sorting at an IC manufacturer site without any additional contacted IC test. 19. The method of claim 1, further comprising providing a homogenous shipment of ICs to a card/system manufacturer without the need for performance sort separation. 20. The method of claim 1, further comprising providing performance matching for many disparate integrated circuits of the at least one integrated circuit which comprise a card or system based upon a common RFID method to minimize on-system performance differences. 21. The method of claim 1, further comprising tuning on-system power supplies using high precision programmable regulation to set voltage in accordance with RFID signatures of the at least one integrated circuit, either as a group or individually. 22. The method of claim 1, further comprising grouping several of the at least one integrated circuit into higher level systems which allows for voltage tailoring and optimization of the system.