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Method of forming a MOS transistor 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/336
출원번호 UP-0701612 (2010-02-08)
등록번호 US-7795101 (2010-10-04)
발명자 / 주소
  • Wang, Hsiang-Ying
  • Chien, Chin-Cheng
  • Hsiao, Tsai-Fu
  • Chien, Ming-Yen
  • Chen, Chao-Chun
출원인 / 주소
  • United Microelectronics Corp.
대리인 / 주소
    Hsu, Winston
인용정보 피인용 횟수 : 6  인용 특허 : 23

초록

A method of forming a MOS transistor, in which, a co-implantation is performed to implant a carbon co-implant into a source region and a drain region or a halo implanted region to effectively prevent dopants from over diffusion in the source region and the drain region or the halo implanted region,

대표청구항

What is claimed is: 1. A method of forming a MOS transistor, comprising: providing a substrate having a gate thereon, a source region and a drain region therein with a channel region under the gate therebetween; pre-amorphizing the source region and the drain region to form amorphized regions; perf

이 특허에 인용된 특허 (23)

  1. Wohlfart, Paulus; Suzuki, Teri; Dharanipragada, Ramalinga M.; Safarova, Alena; Walser, Armin; Strobel, Hartmut, 4-Fluoro-N-indan-2-yl benzamide and its use as a pharmaceutical.
  2. Yung Fu Chong SG; Kin Leong Pey SG; Alex See SG, Activating source and drain junctions and extensions using a single laser anneal.
  3. Park Heemyong ; Mocuta Anda C. ; Rausch Werner, CMOS device structures and method of making same.
  4. Nandakumar, Mahalingam; Zhao, Song; Jain, Amitabh, CMOS fabrication process.
  5. Ju Dong-Hyuk ; Luning Scott, CMOS processing employing zero degree halo implant for P-channel transistor.
  6. Tan,Chung Foong; Liu,Jinping; Lee,Hyeok Jae; Indajang,Bangun; Chor,Eng Fong; Ong,Shiang Yang, End of range (EOR) secondary defect engineering using chemical vapor deposition (CVD) substitutional carbon doping.
  7. Tan,Chung Foong; Liu,Jinping; Lee,Hyeok Jae; Indajang,Bangun; Chor,Eng Fong; Ong,Shiang Yang, End of range (EOR) secondary defect engineering using substitutional carbon doping.
  8. Chidambaram, P. R.; Chatterjee, Amitava; Chakravarthi, Srinivasan, Fabrication of abrupt ultra-shallow junctions using angled PAI and fluorine implant.
  9. Kohli, Puneet; Mehrotra, Manoj; Tang, Shaoping, High threshold NMOS source-drain formation with As, P and C to reduce damage.
  10. Obradovic, Borna; Ekbote, Shashank; Visokay, Mark, MOS device and process having low resistance silicide interface using additional source/drain implant.
  11. Babich, Katherina; Bailey, Todd C.; Conti, Richard A.; Deschner, Ryan P., Mask forming and implanting methods using implant stopping layer and mask so formed.
  12. Chu, Wei Kan; Shao, Lin, Method for shallow dopant distribution.
  13. Chu,Wei Kan; Shao,Lin; Lu,Xinming; Liu,Jiarui; Wang,Xuemei, Method for shallow dopant distribution.
  14. Chau Robert S. ; Jan Chia-Hong ; Packan Paul ; Taylor Mitchell C., Method of forming a transistor.
  15. Graoui,Houda; Foad,Majeed Ali; Al Bayati,Amir, Method of ion implantation to reduce transient enhanced diffusion.
  16. Kim, Yihwan; Foad, Majeed A.; Cho, Yonah; Ye, Zhiyuan; Zojaji, Ali; Sanchez, Errol, Method of ultra-shallow junction formation using Si film alloyed with carbon.
  17. Bu, Haowen; Bushman, Scott Gregory; Chidambaram, Periannan, Methodology of implementing ultra high temperature (UHT) anneal in fabricating devices that contain sige.
  18. Chen,Chien Hao; Nieh,Chun Feng; Mai,Karen; Lee,Tze Liang, Profile confinement to improve transistor performance.
  19. Gardner Mark I. ; Fulford H. Jim ; Wristers Derick J., Reduction of dopant diffusion by the co-implantation of impurities into the transistor gate conductor.
  20. Krull, Wade A.; Horsky, Thomas N., System and method for the manufacture of semiconductor devices by the implantation of carbon clusters.
  21. Arevalo, Edwin A.; Hatem, Christopher R.; Renau, Anthony; England, Jonathan Gerald, Techniques for forming shallow junctions.
  22. Lee Kam Leung, Ultra-shallow semiconductor junction formation.
  23. Lee, Kam Leung, Ultra-shallow semiconductor junction formation.

이 특허를 인용한 특허 (6)

  1. Lin, Yangkui; Chen, Zhihao, Method for fabricating an NMOS transistor.
  2. Pradhan, Nilay A.; Colombeau, Benjamin; Gossmann, Hans-Joachim L., Method for improving fin isolation.
  3. Joshi, Manoj; van Meer, Johannes Marinus; Eller, Manfred, Methods to improve FinFet semiconductor device behavior using co-implantation under the channel region.
  4. Jensen, Jacob; Ghani, Tahir; Liu, Mark Y.; Kennel, Harold; James, Robert, Pulsed laser anneal process for transistor with partial melt of a raised source-drain.
  5. Jensen, Jacob; Ghani, Tahir; Liu, Mark Y.; Kennel, Harold; James, Robert, Pulsed laser anneal process for transistors with partial melt of a raised source-drain.
  6. Jensen, Jacob; Ghani, Tahir; Liu, Mark Y.; Kennel, Harold; James, Robert, Pulsed laser anneal process for transistors with partial melt of a raised source-drain.
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