초록 ▼

The present invention relates to an inter-sequence permutation (ISP) encoder. The ISP encoder comprises: a receiving means to receive an information bit sequence input; a first outputting means for outputting a first code bit output; a second outputting means for outputting a second code bit sequenc

The present invention relates to an inter-sequence permutation (ISP) encoder. The ISP encoder comprises: a receiving means to receive an information bit sequence input; a first outputting means for outputting a first code bit output; a second outputting means for outputting a second code bit sequence output; a bit-adding means coupled to the receiving means, the bit-adding means processing the received information bit sequence input prior to any subsequent processing in the ISP encoder; a first convolutional code encoder coupled between the bit-adding means and the first outputting means; a second convolutional code encoder; and an inter-sequence permutation interleaver coupled between the bit-adding means and the second convolutional code encoder. The second convolutional code encoder is coupled between the inter-sequence permutational interleaver and the second outputting means. Further, the ISP encoder comprises a third outputting means coupled to the bit-adding means to output a third code bit output or directly coupled to the receiving means. Alternatively, the ISP encoder comprises a fourth outputting means coupled to the inter-sequence permutation interleaver to output a fourth code bit sequence output.

대표청구항 ▼

What is claimed is: 1. An inter-sequence permutation encoder, at least comprising: a receiving means for receiving an information bit sequence input; a first outputting means for outputting a first code bit sequence output; a second outputting means for outputting a second code bit sequence output;

What is claimed is: 1. An inter-sequence permutation encoder, at least comprising: a receiving means for receiving an information bit sequence input; a first outputting means for outputting a first code bit sequence output; a second outputting means for outputting a second code bit sequence output; a bit-adding means coupled to the receiving means, wherein the bit-adding means processing the received information bit sequence input prior to any subsequent processing of the received information bit sequence input in the inter-sequence permutation encoder; a first convolutional code encoder coupled between the bit-adding means and the first outputting means; and a second convolutional code encoder coupled to the second outputting means; and an inter-sequence permutation interleaver coupled between the bit-adding means and the second convolutional code encoder, wherein the first and second convolutional code encoders perform as least one of the following methods: tail-biting convolutional encoding, tail-padding convolutional code encoding. 2. The inter-sequence permutation encoder as claimed in claim 1, further comprising a third outputting means coupled to the bit-adding means to output a third code bit sequence output. 3. The inter-sequence permutation encoder as claimed in claim 2, wherein the third outputting means performs a deleting operation in order to eliminate bits added by the bit-adding means. 4. The inter-sequence permutation encoder as claimed in claim 3, wherein the third code bit sequence output undergoes at least an additional puncturing operation. 5. The inter-sequence permutation encoder as claimed in claim 2, wherein the third code bit sequence output undergoes at least an additional deleting operation. 6. The inter-sequence permutation encoder as claimed in claim 1, further comprising a third outputting means coupled to the receiving means to output a third code bit sequence output. 7. The inter-sequence permutation encoder as claimed in claim 6, wherein the third code bit sequence output undergoes at least an additional deleting operation. 8. The inter-sequence permutation encoder as claimed in claim 1, further comprising a fourth outputting means coupled to the inter-sequence permutation interleaver to output a fourth code bit sequence output. 9. The inter-sequence permutation encoder as claimed in claim 8, wherein the fourth outputting means performs a deleting operation in order to eliminate bits added by the bit-adding means. 10. The inter-sequence permutation encoder as claimed in claim 9, wherein the fourth code bit sequence output undergoes at least an additional puncturing operation. 11. The inter-sequence permutation encoder as claimed in claim 8, wherein the fourth code bit sequence output undergoes at least an additional deleting operation. 12. The inter-sequence permutation encoder as claimed in claim 1, wherein methods adopted by the convolutional code encoders are replaced by at least one of the following methods: Reed-Muller code and BCH code. 13. The inter-sequence permutation encoder as claimed in claim 12, wherein the first or second code bit sequence output undergoes at least an additional puncturing operation. 14. The inter-sequence permutation encoder as claimed in claim 12, wherein the first code bit sequence output undergoes at least an additional puncturing operation. 15. The inter-sequence permutation encoder as claimed in claim 12, wherein the second code bit sequence output undergoes at least an additional puncturing operation. 16. The inter-sequence permutation encoder as claimed in claim 1, wherein sequences processed after and before the inter-sequence permutation interleaver are separately encoded. 17. The inter-sequence permutation encoder as claimed in claim 1, wherein the first and second outputting means perform deleting operations in order to eliminate bits added by the bit-adding means. 18. The inter-sequence permutation encoder as claimed in claim 1, wherein the first and second code bit sequence outputs undergo at least an additional puncturing operation. 19. The inter-sequence permutation encoder as claimed in claim 1, wherein the second outputting means performs deleting operations in order to eliminate bits added by the bit-adding means. 20. The inter-sequence permutation encoder as claimed in claim 1, wherein the first outputting means performs deleting operations in order to eliminate bits added by the bit-adding means. 21. The inter-sequence permutation encoder as claimed in claim 1, wherein the first code bit sequence output undergoes at least an additional puncturing operation. 22. The inter-sequence permutation encoder as claimed in claim 1, wherein the second code bit sequence output undergoes at least an additional puncturing operation. 23. An inter-sequence permutation encoder, at least comprising: a receiving means for receiving an information bit sequence input; a first outputting means for outputting a first code bit sequence output; a second outputting means for outputting a second code bit sequence output; a bit-adding means coupled to the receiving means, wherein the bit-adding means processes the received information bit sequence input prior to any subsequent processing of the received information bit sequence input in the inter-sequence permutation encoder; a first convolutional code encoder coupled between the receiving means and the first outputting means; a second convolutional code encoder coupled to the second outputting means; and an inter-sequence permutation interleaver coupled between the bit-adding means and the second convolutional code encoder, wherein the first and second convolutional code encoders perform as least one of the following methods: tail-biting convolutional encoding, tail-padding convolutional code encoding. 24. The inter-sequence permutation encoder as claimed in claim 23, further comprising a third outputting means coupled to the receiving means to output a third code bit sequence output. 25. The inter-sequence permutation encoder as claimed in claim 24, wherein the third code bit sequence output undergoes at least an additional puncturing operation. 26. The inter-sequence permutation encoder as claimed in claim 23, further comprising a fourth outputting means coupled to the inter-sequence permutation interleaver to output a fourth code bit sequence output. 27. The inter-sequence permutation encoder as claimed in claim 26, wherein the fourth outputting means performs a deleting operation in order to eliminate bits added by the bit-adding means. 28. The inter-sequence permutation encoder as claimed in claim 27, wherein the fourth code bit sequence output undergoes at least an additional puncturing operation. 29. The inter-sequence permutation encoder as claimed in claim 23, wherein methods adopted by the convolutional code encoders are replaced by at least one of the following methods: Reed-Muller code and BCH code. 30. The inter-sequence permutation encoder as claimed in claim 23, wherein sequences processed after and before the inter-sequence permutation interleaver are separately encoded. 31. The inter-sequence permutation encoder as claimed in claim 23, wherein the second outputting means performs a deleting operation in order to eliminate bits added by the bit-adding means. 32. The inter-sequence permutation encoder as claimed in claim 31, wherein the first or second code bit sequence output undergoes at least an additional puncturing operation. 33. The inter-sequence permutation encoder as claimed in claim 31, wherein the first code bit sequence output undergoes at least an additional puncturing operation. 34. The inter-sequence permutation encoder as claimed in claim 31, wherein the second code bit sequence output undergoes at least an additional puncturing operation.