Parallel decoder for ultrawide bandwidth receiver
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IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H03M-013/23
H03M-013/41
출원번호
UP-0024804
(2004-12-30)
등록번호
US-7797618
(2010-10-04)
발명자
/ 주소
Wang, Bo
Macias, Adrian R.
출원인 / 주소
Freescale Semiconductor, Inc.
인용정보
피인용 횟수 :
2인용 특허 :
9
초록▼
A method (700) and apparatus (600) are described for performing parallel decoding in connection with 2M-1 parallel ACS unit in ACS unit (110), track buffer (112) and voting unit (114) in an Ultrawide Bandwidth (UWB) receiver having a parallel trellis decoder for decoding a message sequence encoded a
A method (700) and apparatus (600) are described for performing parallel decoding in connection with 2M-1 parallel ACS unit in ACS unit (110), track buffer (112) and voting unit (114) in an Ultrawide Bandwidth (UWB) receiver having a parallel trellis decoder for decoding a message sequence encoded according to a convolutional code. Outputs from the track buffer can be input to a voting unit (114) where a voting scheme can be applied and a decision rendered as to the originally transmitted message sequence.
대표청구항▼
What is claimed is: 1. An integrated circuit capable of conducting a decoding operation on a received sequence of k symbols, the received sequence presumed to include an encoded message sequence of n symbols encoded according to a convolutional code of rate n/k, having a constraint K, and having 2M
What is claimed is: 1. An integrated circuit capable of conducting a decoding operation on a received sequence of k symbols, the received sequence presumed to include an encoded message sequence of n symbols encoded according to a convolutional code of rate n/k, having a constraint K, and having 2M code states, where M is equal to K−1, the received sequence received according to a symbol rate associated with the encoded message sequence, the integrated circuit comprising: 2M-1 parallel connected Add Compare Select (ACS) elements associated with the 2M code states configured to: add a number of branch metric values associated with the received sequence to previous path metrics to form added metrics, compare the added metrics, and select a surviving path metric to form a selected surviving path metric; a track buffer track buffer including 2M path registers configured to be capable of storing decisions indicative of the respective selected surviving path metrics from the 2M-1 parallel connected ACS elements; and a voting unit configured to be capable of generating a decision bit based on the contents of the 2M path registers by voting for the decision bit according to a voting protocol, wherein each of the 2M-1 parallel connected ACS elements includes two path metric output lines providing ACS decision signals and two path feedback lines providing feedback signals, wherein the two path metric output lines in each of the 2M-1 parallel connected ACS elements are connected to a track buffer, wherein the two path feedback lines in each of the 2M-1 parallel connected ACS elements are respectively connected directly as input lines to two different ACS elements selected from the 2M-1 parallel connected ACS elements, wherein the decoding operation includes a maximum a posteriori (MAP) decoding operation. 2. An integrated circuit, as recited in claim 1, wherein: the branch metrics associated with the received code symbol include: b2j,j(r(t)), b2j,j+2M-1(r(t)) and b2j+1,j+2M-1 (r(t)), b2j+1,j (r(t)); each of the 2M parallel ACS element has two Add portions; and one of the two Add portions adds b2j,j(r(t)), b2j,j+2M-1 (r(t)) to a first path metric P2j(t−1) and an other of the two Add portions adds b2j+1,j+2M-1 (r(t)), b2j+1,j (r(t)) to a second path metric P2j+1(t−1) to form the added metrics. 3. An integrated circuit, as recited in claim 1, wherein the previous path metrics include 2M output values associated with the 2M-1 parallel connected ACS units. 4. An integrated circuit, as recited in claim 1, wherein K=6. 5. An integrated circuit, as recited in claim 1, wherein the feedback signals are each one of a previous path metric value, a branch metric value, or a set initialization state input. 6. An integrated circuit, as recited in claim 1, wherein the voting unit, in being configured to be capable of generating a decision bit is further configured to generate the decision bit by cycling the each of the 2M path registers around 100 to around 150 times and wherein the voting protocol includes generating the decision bit based on the contents of a majority of the 2M path registers after the cycling. 7. A method for decoding a received sequence of k symbols, the received sequence presumed to include an encoded message sequence of n symbols encoded according to a convolutional code of rate n/k, having a constraint K, and having 2M code states, where M is equal to K−1, the sequence received according to a symbol rate, the method comprising: performing, substantially in parallel, 2M-1 current Add Compare Select (ACS) operations associated with the 2M code states and outputting 2M path metrics to form 2M path metric outputs; generating 2M feedback outputs based on the 2M-1 current ACS operations; providing the 2M path metric outputs to control operation of a track buffer; providing the 2M feedback outputs directly as inputs to future ACS operations; storing decisions indicative of 2M path metric outputs in 2M path registers associated with the track buffer; and generating a decision bit by applying a voting procedure to a decision related content associated with each of the 2M path registers, wherein the decoding includes maximum a posteriori (MAP) decoding. 8. A method, as recited in claim 7, wherein K=6. 9. A method, as recited in claim 7, wherein the feedback outputs are each one of a previous path metric value, a branch metric value, or a set initialization state input. 10. A method, as recited in claim 7, wherein: the generating the decision bit further includes cycling the each of the 2M path registers around 100 to around 150 times; and the voting procedure includes generating the decision bit based on the contents of a majority of the 2M path registers after the cycling. 11. A method, as recited in claim 7, wherein the performing substantially in parallel, the 2M-1 current Add Compare Select (ACS) operations includes: adding branch metrics associated with the received sequence and 2M previous path metrics to form added metrics, comparing the added metrics, and selecting a surviving path metric to form a selected surviving path metric. 12. A method, as recited in claim 11, wherein the previous path metrics include the path metric outputs. 13. An apparatus configured to be capable of conducting a decoding operation on received sequence of k symbols, the received sequence presumed to include an encoded message sequence of n symbols encoded according to a convolutional code of rate n/k, the convolutional code having a constraint K and 2M code states, where M=K−1, the apparatus comprising: a memory, and a processor coupled to the memory, the processor configured to: input the received sequence according to a symbol rate associated with the message sequence; perform, substantially in parallel, 2M-1 current Add Compare Select (ACS) operations associated with the 2M code states; generate 2M path metric outputs based on the 2M-1 current ACS operations; generate 2M feedback outputs based on the 2M-1 current ACS operations; provide the 2M feedback outputs directly as input signals for future ACS operations; store decisions indicative of the 2M path metric outputs in 2M path registers allocated in the memory; and generate a decision bit based on a voting procedure applied to the 2M path registers, wherein the decoding operation includes a maximum a posteriori (MAP) decoding operation. 14. A method, as recited in claim 13, wherein K=6. 15. An apparatus, as recited in claim 13, wherein the processor, in the performing, substantially in parallel, the 2M-1 current ACS operations, is further configured to: add branch metrics associated with the received sequence to 2M previous path metrics to form added metrics, compare the added metrics, and select a surviving path metric to form a selected surviving path metric. 16. An apparatus, as recited in claim 13, wherein the feedback outputs are each one of a previous path metric value, a branch metric value, or a set initialization state input. 17. An apparatus, as recited in claim 13, wherein: the processor, in the generating the decision bit is further configured to cycle the each of the 2M path registers around 100 to around 150 spin cycles; and the voting procedure includes the generating the decision bit based on the contents of a majority of the 2M path registers after the cycling.
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이 특허에 인용된 특허 (9)
Syed Aon Mujtaba, Area-efficient convolutional decoder.
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