초록 ▼

A pad (20) is electrically connected to a first I/O cell (14) while also physically overlying active circuitry of a second I/O cell (16). Note that although the pad (20) overlies the second I/O cell (16), the pad (20) is not electrically connected to the I/O cell (16). Such a pattern may be replicat

A pad (20) is electrically connected to a first I/O cell (14) while also physically overlying active circuitry of a second I/O cell (16). Note that although the pad (20) overlies the second I/O cell (16), the pad (20) is not electrically connected to the I/O cell (16). Such a pattern may be replicated in any desired manner so that the I/O cells (e.g. 300-310) may have a finer pitch than the corresponding pads (320-324 and 330-335). In addition, the size of the pads may be increased (e.g. pad 131 may be bigger than pad 130) while the width “c” of the I/O cells (132-135) does not have to be increased. Such a pattern (e.g. 500) may be arranged so that the area required in one or more dimensions may be minimized.

대표청구항 ▼

The invention claimed is: 1. An integrated circuit die, comprising: a first bond pad; a second bond pad; a third bond pad; a fourth bond pad; a first probe region electrically coupled to the fourth bond pad; a fifth bond pad; a sixth bond pad; a seventh bond pad, wherein the first probe region and

The invention claimed is: 1. An integrated circuit die, comprising: a first bond pad; a second bond pad; a third bond pad; a fourth bond pad; a first probe region electrically coupled to the fourth bond pad; a fifth bond pad; a sixth bond pad; a seventh bond pad, wherein the first probe region and all of the first, second, third, fourth, fifth, sixth, and seventh bond pads are arranged according to a hexagonal pattern as viewed from a top down perspective and wherein the fourth bond pad is a regular hexagon share having sides equal in length and defining equal angles, and wherein the first probe region is a hexagon shape that is not the regular hexagon shape; and a first I/O cell; wherein a maximum bond pad width of the fifth bond pad is greater than a maximum I/O cell width of the first I/O cell, wherein the maximum I/O cell width of the first I/O cell and the maximum bond pad width of the fifth bond pad are measured along parallel lines, wherein the fifth bond pad overlies, as viewed from the top down perspective, a first portion of the first I/O cell, and wherein the sixth bond pad overlies, as viewed from the top down perspective, a second portion of the first I/O cell. 2. The integrated circuit die of claim 1, further comprising: a second I/O cell, wherein the maximum bond pad width of the fifth bond pad is greater than a maximum I/O cell width of the second I/O cell, wherein the maximum I/O cell width of the second I/O cell and the maximum bond pad width of the fifth bond pad are measured along parallel lines. 3. The integrated circuit die of claim 1, wherein the fifth bond pad is electrically coupled to the first I/O cell and the sixth bond pad is not electrically coupled to the first I/O cell. 4. The integrated circuit die of claim 1, further comprising a second probe region adjacent to at least one of the first, second, and third bond pads, wherein the second probe region is hexagonally shaped. 5. The integrated circuit die of claim 2, wherein the second I/O cell comprises active circuitry selected from a group consisting of input circuitry for directly receiving a signal from one of the first bond pad, second bond pad, and third bond pad and output circuitry for directly providing a signal to the one of the first bond pad, second bond pad, and third bond pad. 6. The integrated circuit die of claim 5, wherein at least one of the first bond pad, second bond pad, and third bond pad is connected to the active circuitry of the second I/O cell with a conductive via extending into the integrated circuit die from the at least one of the first bond pad, second bond pad, and third bond pad. 7. The integrated circuit of claim 1, wherein each of the first, second, and third bond pads are regular hexagons having sides substantially equal in length and defining substantially equal angles. 8. An integrated circuit die, comprising: a plurality of bond pads arranged according to a hexagonal pattern as viewed from a top down perspective, wherein at least five bond pads of the plurality of bond pads form at least part of a hexagon having six corners and six edges, wherein the centers of the at least five bond pads of the plurality of bond pads align with five of the six corners of the hexagon, wherein the hexagon is a regular hexagon having edges equal in length; an underlying metal layer below the plurality of bond pads; and a plurality of I/O cells, wherein a first bond pad of the at least five bond pads of the plurality of bond pads is connected to active circuitry of a first I/O cell of the plurality of I/O cells with a via interconnect extending to the underlying metal layer, wherein a second bond pad of the at least five bond pads overlies at least a portion of the first I/O cell as viewed from the top down perspective, and wherein the second bond pad is not electrically coupled to the first I/O cell. 9. The integrated circuit die of claim 8, each bond pad of the plurality of bond pads is connected to active circuitry of a corresponding I/O cell of the plurality of I/O cells with a via interconnect extending to the underlying metal. 10. The integrated circuit die of claim 8, wherein a center of at least one bond pad of the plurality of bond pads aligns with a center of the hexagon, and wherein the at least one bond pad of the plurality of bond pads that aligns with the center of the hexagon overlaps no other of the plurality of bond pads. 11. The integrated circuit die of claim 8, wherein the six edges of the hexagon define substantially equal angles. 12. The integrated circuit die of claim 8, wherein at least one bond pad of the plurality of bond pads has a probe region as an extension of the at least one bond pad. 13. The integrated circuit die of claim 8, wherein a maximum bond pad width across each of the plurality of bond pads is greater than a maximum I/O cell width of an I/O cell of the plurality of I/O cells, each maximum bond pad width and the maximum I/O cell width measured along parallel lines. 14. The integrated circuit die of claim 8, wherein a third bond pad of the at least five bond pads is connected with a second via interconnect to circuitry selected from a group consisting of power circuitry and ground circuitry. 15. The integrated circuit die of claim 8, wherein each of the at least five bond pads are regular hexagons having sides substantially equal in length and defining substantially equal angles. 16. A single integrated circuit die, comprising: a plurality of bond pads arranged according to a regular hexagon pattern, wherein at least five bond pads of the plurality of bond pads form at least part of a first regular hexagon having six corners and six edges, wherein the centers of the at least five bond pads of the plurality of bond pads align with five of the six corners of the first regular hexagon; core circuitry; and a die edge of the single integrated die, wherein the at least five bond pads are located between the core circuitry and the die edge of the single integrated circuit die, wherein at least one edge of the six edges of the first regular hexagon is perpendicular to a first portion of the die edge nearest to the at least five bond pads. 17. The integrated circuit die of claim 16, wherein at least five other bond pads of the plurality of bond pads form at least part of a second regular hexagon having six corners and six edges, wherein the centers of the at least five other bond pads of the plurality of bond pads align with five of the six corners of the second regular hexagon, and wherein the at least five other bond pads are located between the core circuitry and the die edge, wherein at least one edge of the six edges of the second regular hexagon is substantially perpendicular to a second portion of the die edge nearest to the at least five other bond pads, the first portion of the die edge being perpendicular to the second portion of the die edge. 18. The integrated circuit die of claim 16, wherein a first bond pad of the at least five bond pads which form at least part of the first regular hexagon is coupled to a second bond pad of the at least five other bond pads which form at least part of the second regular hexagon by way of a trace. 19. The integrated circuit die of claim 16, further comprising: a plurality of I/O cells, wherein a first bond pad of the plurality of bond pads is connected to active circuitry of a corresponding I/O cell of the plurality of I/O cells, wherein at least a portion of the plurality of bond pads overlies, from a top view perspective, at least a portion of the plurality of I/O cells, and wherein a maximum bond pad width across the first bond pad is greater than a maximum I/O cell width across the corresponding I/O cell of the plurality of I/O cells, the maximum bond pad width and corresponding maximum I/O cell width measured along substantially parallel lines. 20. The integrated circuit die of claim 16, wherein at least one bond pad of the plurality of bond pads has a probe region as an extension of the at least one bond pad.