초록 ▼

A processor executes a program to calculate values of the internal resistance R of a battery and updates a database of parameters defining the dependence of internal resistance on the battery state of charge (SOC) and temperature. The database is utilized to obtain the information needed to make acc

A processor executes a program to calculate values of the internal resistance R of a battery and updates a database of parameters defining the dependence of internal resistance on the battery state of charge (SOC) and temperature. The database is utilized to obtain the information needed to make accurate remaining run-time calculations. The processor may also execute a program to effectuate entry of a database into memory representative of characteristics of the battery including values of measured open circuit voltages (OCV) of the battery and determinations of “starting SOC” values that correspond to the most recently measured values of OCV after the battery has stabilized. The processor may also execute programs to determine the present SOC of the battery, the present battery capacity, and the remaining run-time of the device powered by the battery.

대표청구항 ▼

The invention claimed is: 1. A method of determining a true internal resistance R of a battery when the battery is inserted into a user device which draws current from the battery comprising: providing a connection to receive voltage from a battery which will draw current from the battery; determin

The invention claimed is: 1. A method of determining a true internal resistance R of a battery when the battery is inserted into a user device which draws current from the battery comprising: providing a connection to receive voltage from a battery which will draw current from the battery; determining an initial voltage, V0, upon insertion of the battery; determining an initial estimate of internal resistance of a battery; determining an initial current, I0, upon insertion of the battery; determining a state of charge for the battery using the initial estimate internal resistance of the battery and the initial current; determining a state of charge, SOC1, associated with a measured relaxed state voltage of the battery; determining a startup state of charge, SOC0, from SOC1, a charge/discharge rate Q1, and a maximum battery charge, Qmax; determining an undistorted initial voltage OCV0 for the SOC0; and determining a true value of the internal resistance R from the undistorted initial voltage OCVO, initial voltage VO and the initial current IO. 2. The method of claim 1 further comprising: integrating the charge/discharge rate over a time t. 3. The method of claim 2, further comprising: determining when a load current drops below a predetermined threshold current, Ith; delaying for a time, t2, or until a rate of voltage change falls below a predetermined threshold rate; and measuring a relaxed state voltage of the battery. 4. The method of claim 1, further comprising: saving R to non-volatile memory and associating R with the inserted battery. 5. The method of claim 1, further comprising: determining a corrected initial voltage upon insertion V01 from R. 6. The method of claim 1, further comprising: determining a corrected state of charge SOCc from R. 7. A system comprising: a processor being couplable to a battery which will draw current from the battery and configured to: determine an initial estimate of internal resistance R of a battery; determine an initial current upon insertion of the battery, I0; determine a state of charge for the battery using the initial estimate of internal resistance of the battery and the initial current; determining an initial voltage, V0, upon insertion of the battery; determine a state of charge, SOC1, associated with the measured relaxed state voltage of the battery; determine a startup state of charge, SOC0, from SOC1, a charge/discharge rate Q1, and a maximum battery charge, Qmax; determine an undistorted initial voltage OCV0 for the SOC0; and determine a true value of the initial resistance R from the undistorted initial voltage OCVO, the initial voltage VO and the initial current IO. 8. The system of claim 7, further comprising memory for saving R and associating R with the inserted battery. 9. The system of claim 8, wherein the processor is further configured to: integrate the charge/discharge rate over a time t. 10. The system of claim 7, wherein the processor is further configured to: determine when a load current drops below a predetermined threshold current, Ith; delay for a time, t2, or until a rate of voltage change falls below a predetermined threshold rate; and measure a relaxed state voltage of the battery. 11. The system of claim 7, wherein the processor is further configured to determine a corrected initial voltage upon insertion V01 from R. 12. The system of claim 7, wherein the processor is further configured to determine a corrected state of charge SOCc from R. 13. A system comprising: means couplable to a battery which will draw current from the battery for determining an initial estimate of internal resistance of a battery; means for determining an initial current upon insertion of the battery, I0; means for determining a state of charge for the battery using the internal resistance of the battery and the initial current; means for determining an initial voltage, V0, upon insertion of the battery; means for monitoring a steady state current to determine a charge/discharge rate, Q1; means for integrating the charge/discharge rate over a time t; means for determining when a load current drops below a predetermined threshold current, Ith; means for delaying for a time, t2, or until a rate of voltage change falls below a predetermined threshold rate; means for measuring a relaxed state voltage of the battery; means for determining a state of charge, SOC1, associated with the measured relaxed state voltage of the battery; means for determining a startup state of charge, SOC0, from SOC1, Q1, and a maximum battery charge, Qmax; means for determining an undistorted initial voltage OCV0 for the SOC0; means for determining the internal resistance during insertion, R, from OCV0, V0 and I0; and means for determining a corrected initial voltage V01 or a corrected state of charge SOCc upon insertion from R.