IPC분류정보
국가/구분 |
United States(US) Patent
등록
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국제특허분류(IPC7판) |
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출원번호 |
UP-0621359
(2007-01-09)
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등록번호 |
US-7814137
(2010-11-01)
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발명자
/ 주소 |
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출원인 / 주소 |
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대리인 / 주소 |
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인용정보 |
피인용 횟수 :
30 인용 특허 :
251 |
초록
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A programmable logic device can be configured as a finite impulse response (FIR) filter capable of operating in either interpolation mode or decimation mode and of switching between those modes at run time. The FIR filter structure can be mapped onto a specialized processing block of the programmabl
A programmable logic device can be configured as a finite impulse response (FIR) filter capable of operating in either interpolation mode or decimation mode and of switching between those modes at run time. The FIR filter structure can be mapped onto a specialized processing block of the programmable logic device that includes multipliers and adders for adding the products of the multipliers. The FIR filter structure minimizes the number of multipliers used by reusing various calculations that are repeated as a result of the interpolation or decimation operation, using multiplexers or other run-time-controllable selectors to select which current or stored multiplier outputs to use.
대표청구항
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What is claimed is: 1. A programmable logic device configured to include a Finite Impulse Response (FIR) filter structure for selectively operating in one of an interpolation filter mode and decimation filter mode; said programmable logic device having at least one specialized processing block each
What is claimed is: 1. A programmable logic device configured to include a Finite Impulse Response (FIR) filter structure for selectively operating in one of an interpolation filter mode and decimation filter mode; said programmable logic device having at least one specialized processing block each of which includes a plurality of multipliers and circuitry for adding outputs of said multipliers, at least one said specialized processing block being programmably configured as said FIR filter structure, said FIR filter structure comprising: (1) a number N of multipliers, where: N=INT [CT/(snSH)]+1 when MOD [CT/(snSH)]≠0, N=CT/(snSH) when MOD [CT/(snSH)]=0, C=the number of channels, T=the number of taps, s=1 for an asymmetric filter, s=2 for a symmetric filter, n=the interpolation/decimation factor, S=a timesharing factor representing the number of clock cycles available to the system to process one input or output sample, H is a factor that represents whether the case is a fullband case (H=1) or a halfband case (H=2) in which all odd coefficients with the exception of the middle coefficient are zero, MOD [x]=x−INT[x], and INT[x] is the largest integer in x; (2) a sample input and a coefficient input for each of said N multipliers, said coefficient input cycling, during operation of said FIR filter structure, through a plurality of coefficients; (3) at least one circuit for adding outputs of said multipliers to each other; and (4) a respective selectable delay located at least one of (a) before, and (b) after, each said circuit for adding; wherein: selection between said interpolation filter mode and said decimation filter mode occurs during operation of said FIR filter structure; and said selection comprises selection of at least one said respective selectable delay. 2. The configured programmable logic device of claim 1 wherein said FIR filter structure comprises: a first multiplier; a first coefficient register providing one input to said first multiplier and cycling through a first plurality of coefficients; a second multiplier; a second coefficient register providing one input to said second multiplier and cycling through a second plurality of coefficients; and an input sample register chain comprising at least three registers starting at a first input sample register and ending at a last input sample register; wherein: said last input sample register provides a second input to said second multiplier; said FIR filter structure further comprising: a sample multiplexer that selects between said first sample register and said last sample register as a second input to said first multiplier; an output adder having outputs of said first and second multipliers as first and second adder inputs; a first intermediate register for storing a one-clock-cycle-delayed output of said first multiplier; a second intermediate register for storing a two-clock-cycle-delayed output of said first multiplier; an intermediate multiplexer for selecting between said first intermediate register and said second intermediate register as a third adder input of said output adder; an accumulator that accumulates successive outputs of said output adder; and an output multiplexer that selects between said output adder and said accumulator to provide an output of said FIR filter structure. 3. The configured programmable logic device of claim 2 wherein said accumulator comprises a delay for outputting said accumulated adder outputs over more than one clock cycle. 4. The configured programmable logic device of claim 2 wherein: said input sample register chain comprises three registers; and said last input sample register is a third input sample register. 5. The configured programmable logic device of claim 2 wherein each respective one of said first and second coefficient registers cycles through a respective set of two coefficients. 6. The configured programmable logic device of claim 1 wherein said FIR filter structure comprises: a first multiplier; a first coefficient register providing one input to said first multiplier and cycling through a first plurality of coefficients; a second multiplier; a second coefficient register providing one input to said second multiplier and cycling through a second plurality of coefficients; an input sample register chain comprising at least seven registers starting at a first input sample register and ending at a last input sample register; a first input adder providing a second input to said first multiplier; a second input adder providing a second input to said second multiplier; a first input multiplexer selecting a first input to said first input adder and having as inputs said first sample register and said last sample register; a second input multiplexer selecting a second input to said first input adder and having as inputs first and second intermediate sample registers; a third input multiplexer selecting a first input to said second input adder and having as inputs third and fourth intermediate sample registers; a fourth input multiplexer selecting a second input to said second input adder and having as inputs said fourth intermediate sample register and a fifth intermediate sample register; an intermediate multiplexer selecting between output of said second multiplier and a zero input; an output adder having as inputs output of said first multiplier and said intermediate multiplexer; an accumulator that accumulates successive outputs of said output adder; a two-clock-cycle delay having as an input output of said second input adder; and an output multiplexer that selects between said accumulator and said two-clock-cycle delay to provide an output of said FIR filter structure. 7. The configured programmable logic device of claim 6 wherein: said input sample register chain comprises eleven registers; said first intermediate sample register comprises a fourth one of said sample registers; said second intermediate sample register comprises a tenth one of said sample registers; said third intermediate sample register comprises a fifth one of said sample registers; said fourth intermediate sample register comprises a seventh one of said sample registers; and said fifth intermediate sample register comprises a sixth one of said sample registers. 8. The configured programmable logic device of claim 6 wherein each respective one of said first and second coefficient registers cycles through a respective set of two coefficients. 9. A method of programmably configuring a Finite Impulse Response (FIR) filter structure in a programmable logic device, said programmable logic device having at least one specialized processing block each of which includes a plurality of multipliers and circuitry for adding outputs of said multipliers, said method comprising: programmably configuring at least one said specialized processing block as a FIR filter structure; including: (1) programmably configuring said FIR filter structure with a number N of multipliers, where: N=INT [CT/(snSH)]+1 when MOD [CT/(snSH)]≠0, N=CT/(snSH) when MOD [CT/(snSH)]=0 C=the number of channels, T=the number of taps, s=1 for an asymmetric filter, s=2 for a symmetric filter, n=the interpolation/decimation factor, S=a timesharing factor representing the number of clock cycles available to the system to process one input or output sample, H is a factor that represents whether the case is a fullband case (H=1) or a halfband case (H=2) in which all odd coefficients with the exception of the middle coefficient are zero, MOD [x]=x−INT[x], and INT[x] is the largest integer in x; (2) programmably configuring each of said N multipliers to have a sample input and a coefficient input, and programmably configuring said coefficient input to cycle through a plurality of coefficients; (3) programmably configuring at least one circuit for adding outputs of said multipliers to each other; (4) programmably configuring a respective selectable delay located at least one of (a) before, and (b) after, each said circuit for adding; and (5) programmably configuring said FIR filter structure to allow selection between an interpolation filter mode and a decimation filter mode during operation of said FIR filter structure; wherein: said selection comprises selection of at least one said respective selectable delay. 10. The method of claim 9 wherein said programmably configuring said FIR filter structure comprises programmably configuring said FIR filter structure to include: a first multiplier; a first coefficient register providing one input to said first multiplier and cycling through a first plurality of coefficients; a second multiplier; a second coefficient register providing one input to said second multiplier and cycling through a second plurality of coefficients; and an input sample register chain comprising at least three registers starting at a first input sample register and ending at a last input sample register; wherein: said last input sample register provides a second input to said second multiplier; said FIR filter structure further comprising: a sample multiplexer that selects between said first sample register and said last sample register as a second input to said first multiplier; an output adder having outputs of said first and second multipliers as first and second adder inputs; a first intermediate register for storing a one-clock-cycle-delayed output of said first multiplier; a second intermediate register for storing a two-clock-cycle-delayed output of said first multiplier; an intermediate multiplexer for selecting between said first intermediate register and said second intermediate register as a third adder input of said output adder; an accumulator that accumulates successive outputs of said output adder; and an output multiplexer that selects between said output adder and said accumulator to provide an output of said FIR filter structure. 11. The method of claim 10 comprising programmably configuring said accumulator to include a delay for outputting said accumulated adder outputs over more than one clock cycle. 12. The method of claim 10 comprising: programmably configuring said input sample register chain to includes three registers; wherein: said last input sample register is a third input sample register. 13. The method of claim 10 comprising programmably configuring each respective one of said first and second coefficient registers to cycle through a respective set of two coefficients. 14. The method of claim 9 wherein said programmably configuring said FIR filter structure comprises programmably configuring said FIR filter structure to include: a first multiplier; a first coefficient register providing one input to said first multiplier and cycling through a first plurality of coefficients; a second multiplier; a second coefficient register providing one input to said second multiplier and cycling through a second plurality of coefficients; an input sample register chain comprising at least seven registers starting at a first input sample register and ending at a last input sample register; a first input adder providing a second input to said first multiplier; a second input adder providing a second input to said second multiplier; a first input multiplexer selecting a first input to said first input adder and having as inputs said first sample register and said last sample register; a second input multiplexer selecting a second input to said first input adder and having as inputs first and second intermediate sample registers; a third input multiplexer selecting a first input to said second input adder and having as inputs third and fourth intermediate sample registers; a fourth input multiplexer selecting a second input to said second input adder and having as inputs said fourth intermediate sample register and a fifth intermediate sample register; an intermediate multiplexer selecting between output of said second multiplier and a zero input; an output adder having as inputs output of said first multiplier and said intermediate multiplexer; an accumulator that accumulates successive outputs of said output adder; a two-clock-cycle delay having as an input output of said second input adder; and an output multiplexer that selects between said accumulator and said two-clock-cycle delay to provide an output of said FIR filter structure. 15. The method of claim 14 comprising: programmably configuring said input sample register chain to include eleven registers; wherein: said first intermediate sample register comprises a fourth one of said sample registers; said second intermediate sample register comprises a tenth one of said sample registers; said third intermediate sample register comprises a fifth one of said sample registers; said fourth intermediate sample register comprises a seventh one of said sample registers; and said fifth intermediate sample register comprises a sixth one of said sample registers. 16. The method of claim 14 comprising programmably configuring each respective one of said first and second coefficient registers to cycle through a respective set of two coefficients. 17. A data storage medium encoded with machine-executable instructions for performing a method of programmably configuring as a Finite Impulse Response (FIR) filter structure in a programmable logic device, said programmable logic device having at least one specialized processing block each of which includes a plurality of multipliers and circuitry for adding outputs of said multipliers, said instructions comprising: instructions for programmably configuring at least one said specialized processing block as a FIR filter structure; including: (1) instructions for programmably configuring said FIR filter structure with a number N of multipliers, where: N=INT [CT/(snSH)]+1 when MOD [CT/(snSH)]≠0, and N=CT/(snSH) when MOD [CT/(snSH)]=0 C=the number of channels, T=the number of taps, s=1 for an asymmetric filter, s=2 for a symmetric filter, n=the interpolation/decimation factor, S=a timesharing factor representing the number of clock cycles available to the system to process one input or output sample, H is a factor that represents whether the case is a fullband case (H=1) or a halfband case (H=2) in which all odd coefficients with the exception of the middle coefficient are zero, MOD [x]=x−INT[x], and INT[x] is the largest integer in x; (2) instructions for programmably configuring each of said N multipliers to have a sample input and a coefficient input, and programmably configuring said coefficient input to cycle through a plurality of coefficients; (3) instructions for programmably configuring at least one circuit for adding outputs of said multipliers to each other; (4) instructions for programmably configuring a respective selectable delay located at least one of (a) before, and (b) after, each said circuit for adding; and (5) instructions for programmably configuring said FIR filter structure to allow selection between an interpolation filter mode and a decimation filter mode during operation of said FIR filter structure; wherein: said selection comprises selection of at least one said respective selectable delay. 18. The data storage medium of claim 17 wherein said instructions for said programmably configuring said FIR filter structure comprise instructions for programmably configuring said FIR filter structure to include: a first multiplier; a first coefficient register providing one input to said first multiplier and cycling through a first plurality of coefficients; a second multiplier; a second coefficient register providing one input to said second multiplier and cycling through a second plurality of coefficients; and an input sample register chain comprising at least three registers starting at a first input sample register and ending at a last input sample register; wherein: said last input sample register provides a second input to said second multiplier; said FIR filter structure further comprising: a sample multiplexer that selects between said first sample register and said last sample register as a second input to said first multiplier; an output adder having outputs of said first and second multipliers as first and second adder inputs; a first intermediate register for storing a one-clock-cycle-delayed output of said first multiplier; a second intermediate register for storing a two-clock-cycle-delayed output of said first multiplier; an intermediate multiplexer for selecting between said first intermediate register and said second intermediate register as a third adder input of said output adder; an accumulator that accumulates successive outputs of said output adder; and an output multiplexer that selects between said output adder and said accumulator to provide an output of said FIR filter structure. 19. The data storage medium of claim 18 wherein said instructions comprise instructions for programmably configuring said accumulator to include a delay for outputting said accumulated adder outputs over more than one clock cycle. 20. The data storage medium of claim 18 wherein: said instructions comprise instructions for programmably configuring said input sample register chain to includes three registers; including: configuring a third input sample register as said last input sample register. 21. The data storage medium of claim 18 wherein said instructions comprise instructions for programmably configuring each respective one of said first and second coefficient registers to cycle through a respective set of two coefficients. 22. The data storage medium of claim 17 wherein said instructions for said programmably configuring said FIR filter structure comprise instructions for programmably configuring said FIR filter structure to include: a first multiplier; a first coefficient register providing one input to said first multiplier and cycling through a first plurality of coefficients; a second multiplier; a second coefficient register providing one input to said second multiplier and cycling through a second plurality of coefficients; an input sample register chain comprising at least seven registers starting at a first input sample register and ending at a last input sample register; a first input adder providing a second input to said first multiplier; a second input adder providing a second input to said second multiplier; a first input multiplexer selecting a first input to said first input adder and having as inputs said first sample register and said last sample register; a second input multiplexer selecting a second input to said first input adder and having as inputs first and second intermediate sample registers; a third input multiplexer selecting a first input to said second input adder and having as inputs third and fourth intermediate sample registers; a fourth input multiplexer selecting a second input to said second input adder and having as inputs said fourth intermediate sample register and a fifth intermediate sample register; an intermediate multiplexer selecting between output of said second multiplier and a zero input; an output adder having as inputs output of said first multiplier and said intermediate multiplexer; an accumulator that accumulates successive outputs of said output adder; a two-clock-cycle delay having as an input output of said second input adder; and an output multiplexer that selects between said accumulator and said two-clock-cycle delay to provide an output of said FIR filter structure. 23. The data storage medium of claim 22 wherein: said instructions comprise instructions for programmably configuring said input sample register chain to include eleven registers; including: configuring a fourth one of said sample registers as said first intermediate sample register; configuring a tenth one of said sample registers as said second intermediate sample register; configuring a fifth one of said sample registers as said third intermediate sample register; configuring a seventh one of said sample registers as said fourth intermediate sample register; and configuring a sixth one of said sample registers as said fifth intermediate sample register. 24. The data storage medium of claim 22 wherein said instructions comprise instructions for programmably configuring each respective one of said first and second coefficient registers to cycle through a respective set of two coefficients.
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