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Disclosed is a device and method for coding a block low density parity check (LDPC) code having a variable length. The a device and method include receiving an information word; and coding the information word into a block LDPC code according to a first parity check matrix or a second parity check m

Disclosed is a device and method for coding a block low density parity check (LDPC) code having a variable length. The a device and method include receiving an information word; and coding the information word into a block LDPC code according to a first parity check matrix or a second parity check matrix depending on a length to be applied when generating the information word into the block LDPC code.

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What is claimed is: 1. A method for coding a block low density parity check (LDPC) code, the method comprising: coding an information word into a block LDPC code based on one of a first parity check matrix and a second parity check matrix depending on a length to be applied when generating the info

What is claimed is: 1. A method for coding a block low density parity check (LDPC) code, the method comprising: coding an information word into a block LDPC code based on one of a first parity check matrix and a second parity check matrix depending on a length to be applied when generating the information word into the block LDPC code, wherein the first parity check matrix is a parity check matrix generated such that the block LDPC code has a predetermined length, and is satisfied with a predetermined coding rate, and wherein the first parity check matrix includes a predetermined number of partial blocks, each of the partial blocks having a predetermined size. 2. The method of claim 1, wherein the second parity check matrix is a parity check matrix defined by varying a size of the first parity check matrix. 3. The method of claim 1, wherein a predetermined permutation matrix is mapped to each of the partial blocks on a one-to-one basis. 4. The method of claim 3, wherein the second parity check matrix is a parity check matrix generated by determining exponents of non-zero permutation matrices among permutation matrices of the second parity check matrix according to exponents of non-zero permutation matrices among permutation matrices of the first parity check matrix and a size of partial blocks of the second parity check matrix. 5. The method of claim 3, wherein the second parity check matrix has a relation defined by ai′=ai mod Ns′ (for 1≦i≦L) where a1, a2, aL denote exponents of L non-zero permutation matrices among permutation matrices of the first parity check matrix, Ns×Ns (Ns) denotes a size of partial blocks of the first parity check matrix, a1′, a2′, . . . , aL′ denote exponents of L non-zero permutation matrices among permutation matrices of the second parity check matrix, Ns′×Ns′ (Ns′) denotes a size of partial blocks of the second parity check matrix, and ‘mod’ denotes a modulo operation. 6. The method of claim 5, wherein coding the information word into a block LDPC code comprises: determining one of the first parity check matrix and the second parity check matrix according to length; generating a first signal by multiplying the information word by a first partial matrix of the determined parity check matrix; generating a second signal by multiplying the information word by a second partial matrix of the determined parity check matrix; generating a third signal by multiplying the first signal by a matrix multiplication of a third partial matrix and an inverse matrix of a fourth partial matrix of the determined parity check matrix; generating a fourth signal by adding the second signal to the third signal; generating a fifth signal by multiplying the fourth signal by a fifth partial matrix of the determined parity check matrix; generating a sixth signal by adding the second signal to the fifth signal; generating a seventh signal by multiplying the sixth signal by the inverse matrix of the fourth matrix of the determined parity check matrix; and multiplexing the information word, the fourth signal defined as a first parity, and the seventh signal defined as a second parity such that the information word, the first parity and the second parity are mapped to the block LDPC code. 7. The method of claim 6, wherein the first partial matrix and the second partial matrix are partial matrices mapped to an information part associated with an information word in the determined parity check matrix. 8. The method of claim 7, wherein the third partial matrix and the fourth partial matrix are partial matrices mapped to a first parity part associated with a parity, and the fifth partial matrix and the sixth partial matrix are partial matrices mapped to a second parity part associated with the parity. 9. The method of claim 1, wherein the first parity check matrix is expressed as where blocks represent the partial blocks, numbers represent exponents of corresponding permutation matrices, and blocks with no number represent partial blocks to which zero matrices are mapped. 10. The method of claim 1, wherein the first parity check matrix is expressed as where blocks represent the partial blocks, numbers represent exponents of corresponding permutation matrices, and blocks with no number represent partial blocks to which zero matrices are mapped. 11. The method of claim 1, wherein the first parity check matrix is expressed as where blocks represent the partial blocks, numbers represent exponents of corresponding permutation matrices, and blocks with no number represent partial blocks to which zero matrices are mapped. 12. The method of claim 1, wherein the first parity check matrix is expressed as where blocks represent the partial blocks, numbers represent exponents of corresponding permutation matrices, and blocks with no number represent partial blocks to which zero matrices are mapped. 13. An apparatus for coding a block low density parity check (LDPC) code, the apparatus comprising: an encoder for coding an information word into a block LDPC code based on one of a first parity check matrix and a second parity check matrix depending on a length to be applied when generating the information word into the block LDPC code, wherein the first parity check matrix is a parity check matrix generated such that the block LDPC code has a predetermined length, and is satisfied with a predetermined coding rate, and wherein the first parity check matrix includes a predetermined number of partial blocks, each of the partial blocks having a predetermined size. 14. The apparatus of claim 13, wherein the second parity check matrix is a parity check matrix defined by varying a size of the first parity check matrix. 15. The apparatus of claim 13, wherein a predetermined permutation matrix is mapped to each of the partial blocks on a one-to-one basis. 16. The apparatus of claim 15, wherein the second parity check matrix is a parity check matrix generated by determining exponents of non-zero permutation matrices among permutation matrices of second parity check matrix according to exponents of non-zero permutation matrices among permutation matrices of the first parity check matrix and a size of partial blocks of the second parity check matrix. 17. The apparatus of claim 15, wherein the second parity check matrix has a relation defined by ai′=ai mod Ns′ (for 1≦i≦L) where a1, a2, . . . , aL denote exponents of L non-zero permutation matrices among permutation matrices of the first parity check matrix, Ns×Ns (Ns) denotes a size of partial blocks of the first parity check matrix, a1′, a2′, . . . , aL′ denote exponents of L non-zero permutation matrices among permutation matrices of the second parity check matrix, Ns′×Ns′ (Ns′) denotes a size of partial blocks of the second parity check matrix, and ‘mod’ denotes a modulo operation. 18. The apparatus of claim 17, wherein the encoder comprises: a controller for determining one of the first parity check matrix and the second parity check matrix according to length; a first matrix multiplier for multiplying the information word by a first partial matrix of the determined parity check matrix; a second matrix multiplier for multiplying the information word by a second partial matrix of the determined parity check matrix; a third matrix multiplier for multiplying a signal output from the first matrix multiplier by a matrix multiplication of a third partial matrix and an inverse matrix of a fourth partial matrix of the determined parity check matrix; a first adder for adding a signal output from the second matrix multiplier to a signal output from the third matrix multiplier; a fourth matrix multiplier for multiplying a signal output from the first adder by a fifth partial matrix of the determined parity check matrix; a second adder for adding the signal output from the second matrix multiplier to a signal output from the fourth matrix multiplier; a fifth matrix multiplier for multiplying the signal output from the second matrix multiplier by the inverse matrix of the fourth matrix of the determined parity check matrix; and a plurality of switches for multiplexing the information word, the fourth signal defined as a first parity, and the seventh signal defined as a second parity such that the information word, the first parity and the second parity are mapped to the block LDPC code. 19. The apparatus of claim 18, wherein the first partial matrix and the second partial matrix are partial matrices mapped to an information part associated with an information word in the determined parity check matrix. 20. The apparatus of claim 19, wherein the third partial matrix and the fourth partial matrix are partial matrices mapped to a first parity part associated with a parity, and the fifth partial matrix and the sixth partial matrix are partial matrices mapped to a second parity part associated with the parity. 21. The apparatus of claim 13, wherein the first parity check matrix is expressed as where blocks represent the partial blocks, numbers represent exponents of corresponding permutation matrices, and blocks with no number represent partial blocks to which zero matrices are mapped. 22. The apparatus of claim 13, wherein the first parity check matrix is expressed as where blocks represent the partial blocks, numbers represent exponents of corresponding permutation matrices, and blocks with no number represent partial blocks to which zero matrices are mapped. 23. The apparatus of claim 13, wherein the first parity check matrix is expressed as where blocks represent the partial blocks, numbers represent exponents of corresponding permutation matrices, and blocks with no number represent partial blocks to which zero matrices are mapped. 24. The apparatus of claim 13, wherein the first parity check matrix is expressed as where blocks represent the partial blocks, numbers represent exponents of corresponding permutation matrices, and blocks with no number represent partial blocks to which zero matrices are mapped. 25. A method for decoding a block low density parity check (LDPC) code, the method comprising: receiving a signal; and decoding the received signal according to one of a first parity check matrix and a second parity check matrix according to a length of a block LDPC code to be decoded thereby detecting the block LDPC code, wherein the first parity check matrix is a parity check matrix generated such that the block LDPC code has a predetermined length, and is satisfied with a predetermined coding rate, and wherein the first parity check matrix includes a predetermined number of partial blocks, each of the partial blocks having a predetermined size. 26. The method of claim 25, wherein the second parity check matrix is a parity check matrix defined by varying a size of the first parity check matrix. 27. The method of claim 25, wherein a predetermined permutation matrix is mapped to each of the partial blocks on a one-to-one basis. 28. The method of claim 27, wherein the second parity check matrix is a parity check matrix generated by determining exponents of non-zero permutation matrices among permutation matrices of the second parity check matrix according to exponents of non-zero permutation matrices among permutation matrices of the first parity check matrix and a size of partial blocks of the second parity check matrix. 29. The method of claim 28, wherein the second parity check matrix has a relation defined by ai′=ai mod Ns′(for 1≦i≦L) where a1, a2, . . . , aL, denote exponents of L non-zero permutation matrices among permutation matrices of the first parity check matrix, Ns×Ns (Ns) denotes a size of partial blocks of the first parity check matrix, a1′, a2′, . . . , aL′ denote exponents of L non-zero permutation matrices among permutation matrices of the second parity check matrix, Ns′×Ns′ (Ns′) denotes a size of partial blocks of the second parity check matrix, and ‘mod’ denotes a modulo operation. 30. The method of claim 29, wherein decoding the received signal according to the determined parity check matrix thereby detecting the block LDPC code comprises: determining a deinterleaving scheme and an interleaving scheme according to the determined parity check matrix; detecting probability values of the received signal; generating a first signal by subtracting a signal generated in a previous decoding process from the probability values of the received signal; deinterleaving the first signal using the deinterleaving scheme; detecting probability values from the deinterleaved signal; generating a second signal by subtracting the deinterleaved signal from probability values of the deinterleaved signal; and interleaving the second signal using the interleaving scheme, and iterative-decoding the interleaved signal thereby detecting the block LDPC code. 31. The method of claim 25, wherein the first parity check matrix is expressed as where blocks represent the partial blocks, numbers represent exponents of corresponding permutation matrices, and blocks with no number represent partial blocks to which zero matrices are mapped. 32. The method of claim 25, wherein the first parity check matrix is expressed as where blocks represent the partial blocks, numbers represent exponents of corresponding permutation matrices, and blocks with no number represent partial blocks to which zero matrices are mapped. 33. The method of claim 25, wherein the first parity check matrix is expressed as where blocks represent the partial blocks, numbers represent exponents of corresponding permutation matrices, and blocks with no number represent partial blocks to which zero matrices are mapped. 34. The method of claim 25, wherein the first parity check matrix is expressed as where blocks represent the partial blocks, numbers represent exponents of corresponding permutation matrices, and blocks with no number represent partial blocks to which zero matrices are mapped. 35. An apparatus for decoding a block low density parity check (LDPC) the apparatus comprising: a receiver for receiving a signal; and a decoder for decoding the received signal according to one of a first parity check matrix and a second parity check matrix according to a length of a block LDPC code to be decoded thereby detecting the block LDPC code, wherein the first parity check matrix is a parity check matrix generated such that the block LDPC code has a predetermined length, and is satisfied with a predetermined coding rate, and wherein the first parity check matrix includes a predetermined number of partial blocks, each of the partial blocks having a predetermined size. 36. The apparatus of claim 35, wherein the second parity check matrix is a parity check matrix defined by varying a size of the first parity check matrix. 37. The apparatus of claim 35, wherein a predetermined permutation matrix is mapped to each of the partial blocks on a one-to-one basis. 38. The apparatus of claim 37, wherein the second parity check matrix is a parity check matrix generated by determining exponents of non-zero permutation matrices among permutation matrices of the second parity check matrix according to exponents of non-zero permutation matrices among permutation matrices of the first parity check matrix and a size of partial blocks of the second parity check matrix. 39. The apparatus of claim 37, wherein the second parity check matrix has a relation defined in the following equation ai′=ai mod Ns′ (for 1≦i≦L) where a1, a2, . . . , aL denote exponents of L non-zero permutation matrices among permutation matrices of the first parity check matrix, Ns×Ns (Ns) denotes a size of partial blocks of the first parity check matrix, a1′, a2′, . . . , aL′ denote exponents of L non-zero permutation matrices among permutation matrices of the second parity check matrix, Ns′×Ns′ (Ns′) denotes a size of partial blocks of the second parity check matrix, and ‘mod’ denotes a modulo operation. 40. The apparatus of claim 39, wherein the decoder comprises: a first controller for determining the first parity check matrix or the second parity check matrix according to a length of the block LDPC code to be decoded; a variable node decoder for detecting probability values of a received signal by connecting variable nodes according to a weight of each of columns constituting the determined parity check matrix; a first adder for subtracting a signal generated in a previous decoding process from a signal output from variable node decoder; a deinterleaver for deinterleaving a signal output from the first adder using a deinterleaving scheme determined according to the determined parity check matrix; a check node decoder for detecting probability values of a signal output from the deinterleaver by connecting check nodes according to a weight of each of rows constituting the determined parity check matrix; a second adder for subtracting a signal output from the deinterleaver from a signal output from the check node decoder; an interleaver for interleaving a signal output from the second adder using an interleaving scheme determined according to the determined parity check matrix, and outputting the interleaved signal to the variable node decoder and the first adder; and a second controller for controlling the deinterleaving scheme and the interleaving scheme according to the determined parity check matrix. 41. The apparatus of claim 35, wherein the first parity check matrix is expressed as where blocks represent the partial blocks, numbers represent exponents of corresponding permutation matrices, and blocks with no number represent partial blocks to which zero matrices are mapped. 42. The apparatus of claim 35, wherein the first parity check matrix is expressed as where blocks represent the partial blocks, numbers represent exponents of corresponding permutation matrices, and blocks with no number represent partial blocks to which zero matrices are mapped. 43. The apparatus of claim 35, wherein the first parity check matrix is expressed as where blocks represent the partial blocks, numbers represent exponents of corresponding permutation matrices, and blocks with no number represent partial blocks to which zero matrices are mapped. 44. The apparatus of claim 35, wherein the first parity check matrix is expressed as where blocks represent the partial blocks, numbers represent exponents of corresponding permutation matrices, and blocks with no number represent partial blocks to which zero matrices are mapped.