IPC분류정보
국가/구분 |
United States(US) Patent
등록
|
국제특허분류(IPC7판) |
|
출원번호 |
UP-0437385
(2006-05-19)
|
등록번호 |
US-7818540
(2010-11-08)
|
우선권정보 |
GB-0126134.6(2002-10-31) |
발명자
/ 주소 |
- Barlow, Stephen
- Bailey, Neil
- Ramsdale, Timothy
- Plowman, David
- Swann, Robert
|
출원인 / 주소 |
|
대리인 / 주소 |
McAndrews Held & Malloy, Ltd.
|
인용정보 |
피인용 횟수 :
2 인용 특허 :
7 |
초록
▼
A vector processing system for executing vector instructions, each instruction defining multiple value pairs, an operation to be executed and a modifier, the vector processing system comprising a plurality of parallel processing units, each arranged to receive one of said pairs of values and, when s
A vector processing system for executing vector instructions, each instruction defining multiple value pairs, an operation to be executed and a modifier, the vector processing system comprising a plurality of parallel processing units, each arranged to receive one of said pairs of values and, when selected, to implement an operation on said value pair to generate a result, each processing unit comprising at least one flag and being selectable in dependence on a condition defined by said at least one flag, wherein the modifier defines the condition under which the parallel processing unit is individually selected.
대표청구항
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The invention claimed is: 1. A vector processing system comprising: a circuit for receiving an instruction identifying a plurality of operands and specifying an operation, wherein each of the plurality of operands comprises a plurality of bits; a plurality of parallel processing units corresponding
The invention claimed is: 1. A vector processing system comprising: a circuit for receiving an instruction identifying a plurality of operands and specifying an operation, wherein each of the plurality of operands comprises a plurality of bits; a plurality of parallel processing units corresponding to each of said plurality of bits of said plurality of operands, each arranged to generate a result according to the operation on particular one bits of the each of the plurality of operands, wherein a parallel processing unit in the plurality of parallel processing units comprises an accumulator that is selectively operable to accumulate sequential results; and a scalar processing unit for generating a composite result according to the accumulated sequential results and/or the results from a selected number of parallel processing units. 2. The vector processing system of claim 1, wherein the selected number of parallel processing units is determined according to a modifier that defines a condition under which a parallel processing unit is selected. 3. The vector processing system of claim 1, wherein the number of parallel processing units is determined according to a plurality of flags that are associated with the plurality of parallel processing units. 4. The vector processing system of claim 1, wherein the system further comprises a vector register file holding packed data comprising multiple operands. 5. The vector processing system of claim 1, wherein each of the plurality of processing units are arranged to generate a result according to the operation on one or more but not all of the operands in the plurality of operands. 6. The vector processing system of claim 1, wherein the plurality of operands identified by the instruction comprises eight 16-bit operands. 7. The vector processing system of claim 1, wherein the plurality of operands identified by the instruction comprises 16 eight-bit operands. 8. The vector processing system of claim 6, wherein at least some of the operands are associated with a value and one of an address or register, and wherein the instruction does not include the value or the one of the address or register associated with the at least some of the operands. 9. The vector processing system of claim 8, wherein the instruction comprises a plurality of bits indicating whether the instruction is a vector instruction or a scalar instruction. 10. A method for vector processing comprising: identifying a plurality of operands, wherein each of said plurality of operands comprises a plurality of bits; specifying an operation; selecting the number of parallel executions of the operation; executing the operation in parallel on one or more operands in the plurality of operands to generate a plurality of results, wherein executing the operation in parallel further comprises executing the operation with a plurality of parallel processing units corresponding to the plurality of bits of each operand, wherein each of said plurality of parallel processing units executes the operation on corresponding ones of the plurality of bits for each of the plurality of operands; selectively accumulating sequential results from each operation; and generating a composite result according to the accumulated sequential results and/or the plurality of results. 11. The method of claim 10, wherein selecting the number of parallel executions of the operation is based on a modifier that defines a condition under which a parallel processing unit is selected. 12. The method of claim 10, wherein selecting the number of parallel executions of the operation is based on a plurality of flags that are associated with each execution of the operation. 13. The method of claim 10, wherein the plurality of operands are packed in a vector register file. 14. An integrated circuit for vector processing, wherein the integrated circuit comprises: a memory having stored thereon a computer program comprising an instruction stream including a vector instruction, the vector instruction defining multiple operands, wherein each of said multiple operands comprises a plurality of bits, an operation to be executed on the multiple operands, and a modifier; and a vector processing unit which comprises a plurality of parallel processing units corresponding to each of the plurality of bits, wherein each parallel processing unit is arranged to receive a corresponding bit of each operand and to selectively implement said operation, and wherein a parallel processing unit is selected to operate on the basis of a condition defined by at least one flag in the parallel processing unit, and wherein the condition is set by the modifier in the vector instruction, each parallel processing unit in the plurality of parallel processing units comprises an accumulator that is selectively operable to accumulate the results of the parallel processing unit, and wherein more than one result and/or an accumulated result from the plurality of parallel processing units is processed to generate a scalar result. 15. The integrated circuit according to claim 14, wherein each parallel processing unit in the plurality of parallel processing units comprises a plurality of flags, the condition being defined by the state of said plurality of flags. 16. The integrated circuit according to claim 14, wherein the modifier in the vector instruction is a set flag modifier for updating the at least one flag in the plurality of parallel processing units. 17. The integrated circuit according to claim 14, wherein the memory further stores a vector register file holding packed operands, each operand comprising multiple values. 18. The integrated circuit according to claim 14, wherein the modifier of the vector instruction is an accumulate modifier that causes the accumulator to accumulate the results of successive operations of the parallel processing unit.
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