IPC분류정보
국가/구분 |
United States(US) Patent
등록
|
국제특허분류(IPC7판) |
|
출원번호 |
UP-0579037
(2004-06-25)
|
등록번호 |
US-7820523
(2010-11-15)
|
우선권정보 |
FR-04 50889(2004-05-07) |
국제출원번호 |
PCT/EP2004/051255
(2004-06-25)
|
§371/§102 date |
20061030
(20061030)
|
국제공개번호 |
WO05/109509
(2005-11-17)
|
발명자
/ 주소 |
- Andrieu, François
- Ernst, Thomas
- Deleonibus, Simon
|
출원인 / 주소 |
- Commissariat a l'Energie Atomique
|
대리인 / 주소 |
McKenna Long & Aldridge LLP
|
인용정보 |
피인용 횟수 :
1 인용 특허 :
8 |
초록
▼
The invention concerns a micro-electronic device comprising a substrate, a first insulating zone and a second insulating zone laying on said substrate, a first active zone comprising at least one layer made of a first semi-conductor crystalline material, resting on said first insulating zone which i
The invention concerns a micro-electronic device comprising a substrate, a first insulating zone and a second insulating zone laying on said substrate, a first active zone comprising at least one layer made of a first semi-conductor crystalline material, resting on said first insulating zone which insulates it from the substrate, at least one second active zone comprising at least one layer in a second semi-conductor crystalline material, laying on said second insulating zone which insulates it from the substrate, said first semi-conductor crystalline material having a different composition from that of the second semi-conductor crystalline material and/or different crystalline orientation from that of the second semi-conductor crystalline material and/or mechanical strains from that of the second semi-conductor crystalline material.
대표청구항
▼
The invention claimed is: 1. Process for making a micro-electronic device, comprising the following steps: a) forming, on a first substrate and in a vertical direction, at least a first semi-conductor zone made of a first semi-conductor crystalline material, and forming at least a second semi-condu
The invention claimed is: 1. Process for making a micro-electronic device, comprising the following steps: a) forming, on a first substrate and in a vertical direction, at least a first semi-conductor zone made of a first semi-conductor crystalline material, and forming at least a second semi-conductor zone from a second semi-conductor crystalline material different from the first semi-conductor crystalline material, b) covering said first and second semi-conductor zones with an insulating layer, c) assembling a second substrate on said insulating layer, d) eliminating the first substrate, and e) forming a lateral space between the first semi-conductor zone and second semi-conductor zone. 2. Process of claim 1, said first semi-conductor zone being formed by at least one epitaxial growth. 3. Process according to claim 1, said second semi-conductor zone being formed by at least one epitaxial growth. 4. Process of claim 3, said second semi-conductor zone being formed by epitaxial growth on one part of said first semi-conductor zone. 5. Process of claim 4, in which a masking step of a portion of said first semi-conductor zone is carried out prior to said epitaxial growth of the second semi-conductor zone, said second semi-conductor zone being formed on another unmasked portion of said first semi-conductor zone. 6. Process of claim 4, said part of said first semi-conductor zone on which the second semi-conductor zone is formed being eliminated after step d). 7. Process of claim 1, the first and second semi-conductor zones being formed by epitaxial growth on a same layer of material. 8. Process of claims 1, in which part of the first semi-conductor zone is etched through a mask prior to the formation of the second semi-conductor zone, said second semi-conductor zone being then formed at the location of said etched part of said first semi-conductor zone. 9. Process of claims 1, comprising among others the formation of a lateral insulation zone in the lateral space between the two semi-conductor zones. 10. Process of claim 1, the lateral insulation zone being obtained by etching a part of the first substrate and/or at least part of the first semi-conductor zone, and by filling the etched part with an insulating material. 11. Process of claim 10, said filling material of said etched part being the material used in step b) to form said insulating thickness b). 12. Process according to claim 1, the first substrate comprising a semi-conductor block, and at least an etch stop layer covering said semi-conductor block. 13. Process according to claim 1, the first semi-conductor zone being made of one or more semi-conductor layers. 14. Process according to claim 13, the second semi-conductor zone being made of one or more semi-conductor layers. 15. Process according to claim 1, the first substrate being made from a second semi-conductor material. 16. Process according to claim 1, the first substrate being made of Si or Ge or GaAs. 17. Process according to claim 1, the insulating thickness formed during step b) comprising Si3N4 and/or SiO2. 18. Process according to claim 1, comprising among others between steps a) and b), a step for creating the transistor gate on each semi-conductor zone. 19. Process for making a transistor comprising the creation of a micro-electronic device according to claim 1, then the creation of source and drain regions, channel and gate in each-semi-conductor zone. 20. Process according to claim 1, wherein the first and second semi-conductor crystalline materials have different crystalline materials; different crystalline orientations; different crystalline strains; different crystalline materials and orientations; different crystalline materials and strains; different crystalline orientations and strains; or different crystalline materials, orientations, and strain. 21. Process for making a micro-electronic device, comprising the following steps: a) forming, on a first substrate, at least a first semi-conductor zone made of a first semi-conductor crystalline material, and forming at least a second semi-conductor zone from a second semi-conductor crystalline material different from the first semi-conductor crystalline material, b) covering said first and second semi-conductor zones with an insulating layer, wherein the insulating layer is adjacent to the first and the second semi-conductor zones, c) assembling a second substrate on said insulating layer, and d) eliminating the first substrate. 22. Process according to claim 21, wherein the first and second semi-conductor crystalline materials have different crystalline materials; different crystalline orientations; different crystalline strains; different crystalline materials and orientations; different crystalline materials and strains; different crystalline orientations and strains; or different crystalline materials, orientations, and strain. 23. Process according to claim 21, wherein the first and second semi-conductor crystalline materials have different crystalline materials; different crystalline orientations; different crystalline strains; different crystalline materials and orientations; different crystalline materials and strains; different crystalline orientations and strains; or different crystalline materials, orientations, and strain.
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