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Effecting a broadcast with an allreduce operation on a parallel computer 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-015/76
출원번호 UP-0832918 (2007-08-02)
등록번호 US-7827385 (2010-11-22)
발명자 / 주소
  • Almasi, Gheorghe
  • Archer, Charles J.
  • Ratterman, Joseph D.
  • Smith, Brian E.
출원인 / 주소
  • International Business Machines Corporation
대리인 / 주소
    Biggers & Ohanian, LLP
인용정보 피인용 횟수 : 1  인용 특허 : 28

초록

A parallel computer comprises a plurality of compute nodes organized into at least one operational group for collective parallel operations. Each compute node is assigned a unique rank and is coupled for data communications through a global combining network. One compute node is assigned to be a log

대표청구항

What is claimed is: 1. A method for effecting a broadcast with an allreduce operation on a parallel computer, the parallel computer comprising a plurality of compute nodes, the compute nodes organized into at least one operational group of compute nodes for collective parallel operations of the par

이 특허에 인용된 특허 (28)

  1. Scott Steven L. ; Pribnow Richard D. ; Logghe Peter G. ; Kunkel Daniel L. ; Schwoerer Gerald A., Adaptive congestion control mechanism for modular computer networks.
  2. Kato Sadayuki,JPX ; Ishihata Hiroaki,JPX ; Horie Takeshi,JPX ; Inano Satoshi,JPX ; Shimizu Toshiyuki,JPX, Data gathering/scattering system for a plurality of processors in a parallel computer.
  3. Cotter David,GBX ; Tatham Martin C,GBX, Dead reckoning routing of packet data within a network of nodes having generally regular topology.
  4. Hardwick Jonathan C.,GBX, Dynamic load balancing among processors in a parallel computer.
  5. Michael Olivier, Dynamically matching users for group communications based on a threshold degree of matching of sender and recipient predetermined acceptance criteria.
  6. Blumrich,Matthias A.; Chen,Dong; Coteus,Paul W.; Gara,Alan G.; Giampapa,Mark E; Heidelberger,Philip; Kopcsay,Gerard V.; Steinmacher Burow,Burkhard D.; Takken,Todd E., Global interrupt and barrier networks.
  7. Cypher Robert E. (Los Gatos CA) Sanz Jorge L. C. (Los Gatos CA), Hierarchical interconnection network architecture for parallel processing, having interconnections between bit-addressib.
  8. Crosetto Dario B., High-speed, parallel, processor architecture for front-end electronics, based on a single type of ASIC, and method use t.
  9. Flaig Charles M. (Pasadena CA) Seitz Charles L. (San Luis Rey CA), Inter-computer message routing system with each computer having separate routinng automata for each dimension of the net.
  10. Heller Steven K. (Derry NH), Message transfer system and method for parallel computer with message transfers being scheduled by skew and roll functio.
  11. Carmichael Richard D. ; Ward Joel M. ; Winchell Michael A., Method and apparatus for controlling (N+I) I/O channels with (N) data managers in a homogenous software programmable en.
  12. Nilsson Olof E. (Rnninge SEX), Method and apparatus for the connection of a closed ring through a telephone exchange.
  13. Brown, David A., Method and apparatus for wire speed IP multicast forwarding.
  14. Kureya Kimihide,JPX, Method for performing alltoall communication in parallel computers.
  15. Ogasawara Takeshi,JPX ; Komatsu Hideaki,JPX, Method of optimizing recognition of collective data movement in a parallel distributed system.
  16. Stevens Luis F., Method, system and computer program product for managing memory in a non-uniform memory access system.
  17. Frisch Robert Charles, Multicomputer memory access architecture.
  18. Krishnamoorthy Ashok V. (11188 Caminito Rodar San Diego CA 92126) Kiamilev Fouad (c/o UNC Charlotte ; Dept. of EE ; Smith Hall Room 332 Charlotte NC 28223), Packet-switched self-routing multistage interconnection network having contention-free fanout, low-loss routing, and fan.
  19. Yasuda Yoshiko,JPX ; Tanaka Teruo,JPX, Parallel computer system using properties of messages to route them through an interconnect network and to select virtua.
  20. Maddox James L., Parallel computing system.
  21. Hardwick Jonathan C.,GBX, Parallel processing method and system using a lazy parallel data type to reduce inter-processor communication.
  22. Wilkinson Paul Amba ; Dieffenderfer James Warren ; Kogge Peter Michael ; Schoonover Nicholas Jerome, Partitioning of processing elements in a SIMD/MIMD array processor.
  23. Meeker Woodrow L. ; Abercrombie Andrew P., Pattern generation and shift plane operations for a mesh connected computer.
  24. Feisullin Farid ; Naylor Bruce ; Raukumar Ajay ; Rogers Lois, Prediction system for RF power distribution.
  25. Nugent Steven F., Routing resource reserve/release protocol for multi-processor computer systems.
  26. Dunning Dave (Portland OR), Self-timed mesh routing chip with data broadcasting.
  27. Jhanji,Neeraj, Systems for communicating current and future activity information among mobile internet users and methods therefor.
  28. Amemiya, Jiro; Uesugi, Kouki, Video output controller and video card.

이 특허를 인용한 특허 (1)

  1. Archer, Charles J.; Blocksome, Michael A.; Ratterman, Joseph D.; Smith, Brian E., Performing a vector collective operation on a parallel computer having a plurality of compute nodes.
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