초록 ▼

In accordance with one embodiment of the invention, a method and apparatus are provided for obtaining test data from multiples devices under test. This could be accomplished in accordance with one embodiment by outputting from a testing device a test signal for input in parallel to at least two devi

In accordance with one embodiment of the invention, a method and apparatus are provided for obtaining test data from multiples devices under test. This could be accomplished in accordance with one embodiment by outputting from a testing device a test signal for input in parallel to at least two devices under test; inputting in parallel to the testing device at least two response signals, each response signal produced by one of the at least two devices under test; storing the response signals received in parallel in a storage device; and serially outputting the response signals from the storage device.

대표청구항 ▼

What is claimed is: 1. A method of obtaining test data from a plurality of devices under test, said method comprising: outputting from a testing device a first test signal for input in parallel to at least two devices under test; inputting in parallel to said testing device at least two response si

What is claimed is: 1. A method of obtaining test data from a plurality of devices under test, said method comprising: outputting from a testing device a first test signal for input in parallel to at least two devices under test; inputting in parallel to said testing device at least two response signals, each response signal produced by one of said at least two devices under test in response to said first test signal; storing said response signals received in parallel in a storage device; serially outputting said response signals from said storage device. 2. The method as claimed in claim 1 wherein said inputting in parallel to said testing device said at least two response signals comprises: latching each response signal with a dedicated latch. 3. The method as claimed in claim 1 wherein said inputting in parallel to said testing device said at least two response signals comprises: testing each response signal with a dedicated comparator; latching each response signal with a dedicated latch. 4. The method as claimed in claim 1 wherein said storing said response signals received in parallel comprises: reading said response signals in parallel into a serial shifter. 5. The method as claimed in claim 1 wherein said serially outputting said response signals from said storage device comprises: serially outputting said stored response signals to a logic tester. 6. The method as claimed in claim 1 wherein said serially outputting said response signals from said storage device comprises: serially outputting said stored response signals to an error catch ram. 7. The method as claimed in claim 1 wherein said outputting from said testing device said first test signal for input in parallel to said at least two devices under test comprises: generating said first test signal; providing a plurality of devices under test having the same circuit configuration; inputting said first test signal in parallel to the same location at each device under test. 8. An apparatus for obtaining test data from a plurality of devices under test, said apparatus comprising: a test signal generator configured to output from a testing device a first test signal for input in parallel to at least two devices under test; a response signal receiver configured to input in parallel to said testing device at least two response signals, each response signal produced by one of said at least two devices under test in response to said first test signal; a storage device configured to store said response signals received in parallel; a serial output circuit configured to serially output said response signals from said storage device. 9. The apparatus as claimed in claim 8 wherein said response signal receiver for inputting in parallel to said testing device said at least two response signals comprises: a plurality of latches, each of said latches dedicated to latching one of said response signals. 10. The apparatus as claimed in claim 8 wherein response signal receiver configured to input in parallel said at least two response signals comprises: a plurality of comparators, each of said comparators dedicated for testing one of said response signals; a plurality of latches, each of said latches dedicated to one of said response signals. 11. The apparatus as claimed in claim 8 wherein said storage device comprises a serial shifter. 12. The apparatus as claimed in claim 8 and wherein said storage device is coupled with a logic tester configured to test said stored response signals. 13. The apparatus as claimed in claim 8 wherein said storage device is coupled with an error catch ram. 14. The apparatus as claimed in claim 8 wherein said test signal generator is configured to: generate said first test signal; couple with a plurality of devices under test having the same circuit configuration; input said first test signal in parallel to the same location at each device under test. 15. An apparatus for obtaining test data from a plurality of devices under test, said apparatus comprising: means for generating a first test signal for input in parallel to at least two devices under test; means for receiving an input in parallel from at least two response signals, each response signal produced by one of said at least two devices under test in response to said first test signal; means for storing said response signals received in parallel; means for serially outputting said response signals from said means for storing. 16. The apparatus as claimed in claim 15 wherein said means for receiving comprises: a plurality of latches, each of said latches dedicated to latching one of said response signals. 17. The apparatus as claimed in claim 15 wherein said means for receiving comprises: a plurality of comparators, each of said comparators dedicated for testing one of said response signals; a plurality of latches, each of said latches dedicated to one of said response signals. 18. The apparatus as claimed in claim 15 wherein said means for storing comprises a serial shifter. 19. The apparatus as claimed in claim 15 and wherein said means for storing is coupled with a logic tester configured to test said stored response signals. 20. The apparatus as claimed in claim 15 wherein said means for storing is coupled with an error catch ram.